Semiconductor integrated circuit device and layout method of patterns for semiconductor integrated circuit device
AssigneeNEC Electronics Corporation
InventorHideo Sonohara
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit device includes macros and area I/Os. The macros are arranged in optional locations of a first empty area of a gate area in a center portion of a chip, respectively. Each of the area I/Os contains a plurality of area I/O buffers, and is arranged in an optional location of a second empty area of a total area of the gate area and a buffer area in a circumferential portion of the chip. A first macro of the macros is connected with a specific one of the area I/Os. Here, the specific area I/O may be related to the first macro and be arranged in relation to a location for the first macro to be arranged.
Claims16
A semiconductor integrated circuit device comprising:
- macros arranged in optional locations of a first empty area of a gate area in a center portion of a chip, respectively;
- and
- area I/Os, each of which contains a plurality of area I/O buffers, and is arranged in an optional location of a second empty area of a total area of said gate area and a buffer area in a circumferential portion of said chip,
- wherein a first macro of said macros is connected with a specific one of said area I/Os.
A design apparatus of a semiconductor integrated circuit comprising:
- a macro table which stores macro data and specification data, wherein said macro data specifies each of a plurality of macros, and said specification data specifies an area I/O corresponding to each of said plurality of macros, and said area I/O contains a plurality of I/O buffers and is possible to be arranged in an optional location of a first empty area of a gate area and a circumferential portion on a chip, said circumferential portion surrounding said gate area;
- a selection section which refers to said macro table based on data for specifying each of a plurality of design macros and process data for specifying whether said macro needs to carry out high-speed signal processing, to select a high-speed processing macro and said area I/O related to said high-speed macro;
- and
- a layout design section which arranges said high-speed processing macro and said area I/O in predetermined locations on a chip such that said high-speed macro is arranged in a second empty area of said gate area and said area I/O is arranged in said first empty area of said gate area and said buffer area.
A layout method of a semiconductor integrated circuit device, comprising:
- selecting a high-speed processing macro, in which a signal needs to be processed at high speed, and an area I/O related to said high-speed processing macro based on design macro data of each of a plurality of design macros to be laid-out and specification data for specifying whether said design macro is said high-speed processing macro;
- and
- arranging said high-speed processing macro said area I/O on a chip which has a gate area in a center portion and a buffer area in a circumferential portion.
A software product executable by a computer for a layout method of a semiconductor integrated circuit device, said layout method comprising:
- selecting a high-speed processing macro, in which a signal needs to be processed at high speed, and an area I/O related to said high-speed processing macro based on design macro data of each of a plurality of design macros to be laid-out and specification data for specifying whether said design macro is said high-speed processing macro;
- and
- arranging said high-speed processing macro said area I/O on a chip which has a gate area in a center portion and a buffer area in a circumferential portion.
A semiconductor integrated circuit device comprising:
- macros arranged in optional locations of a first empty area of a gate area in a center portion of a chip, respectively;
- area I/Os, each of which contains a plurality of area I/O buffers, and is arranged in an optional location of a second empty area of a total area of said gate area and a buffer area in a circumferential portion of said chip;
- and
- a peripheral I/O provided in a fixed area of said buffer area, and containing a plurality of peripheral I/O buffers,
- wherein a first macro of said macros is connected with a specific one of said area I/Os, and
- a specific one of said plurality of peripheral I/O buffers is connected with a second macro of said macros.
Dependencies are inferred from the claim text.