Structure and manufacturing method of non-volatile semiconductor memory device

A method for manufacturing a cell stack, comprising steps of:

• (a) providing a substrate;
• (b) forming on said substrate an oxide layer, a first conductive layer, a first dielectric layer, and a second conductive layer sequentially;
• (c) etching said second conductive layer, said first dielectric layer, and said first conductive layer for forming a first recess pattern;
• (d) filling said first recess pattern with a second dielectric layer on said oxide layer;
• (e) depositing a third dielectric layer on said second conductive layer and said second dielectric layer;
• (f) depositing a fourth dielectric layer on said third dielectric layer;
• (g) etching said fourth dielectric layer and said third dielectric layer to form a second recess pattern on said second conductive layer;
• (h) depositing a barrier layer on an inner surface of said second recess pattern on said second conductive layer;
• and
• (i) filling said second recess pattern with a third conductive layer.