Semiconductor memory device and a method of manufacturing the same
AssigneeRenesas Technology Corp.
InventorsMasahiro Moniwa, Hiraku Chakihara, Kousuke Okuyama, Yasuhiko Takahashi
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Abstract
A memory cell of a SRAM comprises two drive MISFET and two vertical MISFETs. The p channel vertical MISFET are formed above the n channel drive MISFET. The vertical MISFETs respectively mainly comprise a square pole laminate comprising a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film comprising silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
Claims60
A semiconductor memory device comprising a memory cell including first and second drive MISFETs and first and second vertical MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first drive MISFET and second drive MISFET being cross-coupled,
- wherein said first and second vertical MISFETs are formed higher than said first and second drive MISFETs formed on a principal surface of a semiconductor substrate,
- wherein said first and second vertical MISFETs respectively comprise a source, channel region and drain formed in a laminate in a perpendicular direction from said principal surface of said semiconductor substrate, and a gate electrode formed via a gate insulating film on side walls of said laminate,
- wherein said complementary data lines are formed higher than said first and second vertical MISFETs, and
- wherein one of said source and drain of said first and second vertical MISFETs are respectively electrically connected to said complementary data lines.
A semiconductor memory device comprising a memory cell including first and second drive MISFET and first and second vertical MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first drive MISFET and second drive MISFET being cross-coupled,
- wherein said first and second and vertical MISFET are formed higher than said first and second drive MISFETs formed on a principal surface of a semiconductor substrate,
- wherein said first and second vertical MISFETs respectively comprise a source, channel region and drain formed in a laminate extending in a perpendicular direction from said principal surface of said semiconductor substrate, and a gate electrode formed via a gate insulating film on side walls of said laminate, and
- wherein said first and second vertical MISFETs are perfect depletion type MISFET.
A semiconductor memory device comprising a memory cell including first and second drive MISFETs and first and second vertical MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first drive MISFET and second drive MISFET being cross-coupled,
- wherein said first and second and vertical MISFET are formed higher than said first and second drive MISFETs formed on a principal surface of a semiconductor substrate,
- wherein said first and second vertical MISFETs respectively comprise a source, channel region and drain formed in a laminate in a perpendicular direction from said principal surface of said semiconductor substrate, and a gate electrode formed via a gate insulating film on side walls of said laminate, and
- wherein said gate electrodes of said first and second vertical MISFETs are formed so as to surround said side wall perimeter of said laminate.
A semiconductor memory device comprising a memory cell including first and second drive MISFETs and first and second vertical MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first drive MISFET and second drive MISFET being cross-coupled,
- wherein said first and second and vertical MISFET are formed higher than said first and second drive MISFETs formed on a principal surface of a semiconductor substrate,
- wherein said first and second vertical MISFETs respectively comprise a source, channel region and drain formed in a laminate extending in a perpendicular direction from said principal surface of said semiconductor substrate, and a gate electrode formed via a gate insulating film on side walls of said laminate,
- wherein one of said source and drain of said first vertical MISFET comprises a part which is superficially superimposed on said drain region of said first drive MISFET, and
- wherein one of said source and drain of said second vertical MISFET comprises a part which is superficially superimposed on said drain region of said second drive MISFET.
A semiconductor memory device comprising a memory cell including first and second drive MISFETs and first and second vertical MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first drive MISFET and second drive MISFET being cross-coupled,
- wherein said first and second and vertical MISFET are formed higher than said first and second drive MISFETs formed on a principal surface of a semiconductor substrate,
- wherein said first and second vertical MISFETs respectively comprise a source, channel region and drain formed in a laminate extending in a perpendicular direction from said principal surface of said semiconductor substrate, and a gate electrode formed via a gate insulating film on side walls of said laminate,
- wherein said laminates of said first and second vertical MISFETs are mutually disposed at a distance apart from each other in a first direction,
- wherein said word line is electrically connected to said gate electrodes of said first and second vertical MISFETs, and extends in said first direction so as to cover side walls of said laminate of said first and second vertical MISFETs,
- wherein said complementary data lines are formed higher than said word line said first and second vertical MISFETs, and extend in a second direction perpendicular to said first direction, and
- wherein one of said source and drain of said first and second vertical MISFETs are respectively electrically connected to said complementary data lines.
A semiconductor memory device comprising first and second drive MISFETs and first and second vertical MISFETs disposed at an intersection of a pair of complementary data lines and a word line,
- wherein a pair of cross-coupled interconnections which cross-couple said first drive MISFET and said second drive MISFET formed in a principal surface of a semiconductor substrate, are formed above said first and second drive MISFETs,
- wherein said first and second vertical MISFETs are formed above said cross-coupled interconnections,
- wherein said first and second vertical MISFETs respectively comprise a source, channel region and drain formed in a laminate which extends in a perpendicular direction to said principal surface of said semiconductor substrate, and a gate electrode formed on side walls of said laminate via a gate insulating film,
- wherein said complementary data line is formed above said first and second vertical MISFETs, and
- wherein one of said source and drain of said first and second vertical MISFETs are electrically connected to said complementary data line.
A semiconductor memory device comprising a memory cell including first and second drive MISFETs and first and second vertical MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first drive MISFET and second drive MISFET being cross-coupled,
- wherein said first and second vertical MISFETs are formed above said first and second drive MISFETs formed in a principal surface of a semiconductor substrate,
- wherein said first and second vertical MISFETs respectively comprise a source, channel region and drain formed in a laminate which extends in a perpendicular direction to said principal surface of said semiconductor substrate, and a gate electrode formed on side walls of said laminate via a gate insulating film, and
- wherein a capacitative element is connected to a charge storage node of said cross-couple.
A semiconductor memory device comprising a memory cell including first and second drive MISFETs and first and second vertical MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first drive MISFET and second drive MISFET being cross-coupled,
- wherein a pair of reference voltage lines extend in a first direction,
- wherein said first drive MISFET and second drive MISFET are disposed between said pair of reference voltage lines in a second direction which intersects perpendicularly with said first direction,
- wherein said source of said first drive MISFET is electrically connected to one reference voltage line,
- wherein said source of said second drive MISFET is electrically connected to the other reference voltage line,
- wherein said first and second vertical MISFETs are formed above said first and second drive MISFETs formed in a principal surface of a semiconductor substrate, and
- wherein said first and second vertical MISFETs respectively comprise a source, channel region and drain formed in a laminate extending in a perpendicular direction from said principal surface of said semiconductor substrate, and a gate electrode formed via a gate insulating film on side walls of said laminate.
A semiconductor memory device comprising a memory cell including first and second drive MISFETs and first and second vertical MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first drive MISFET and second drive MISFET being cross-coupled,
- wherein a pair of reference voltage lines extend in a first direction,
- wherein said first drive MISFET and second drive MISFET are disposed between said pair of reference voltage lines in a second direction which intersects perpendicularly with said first direction,
- wherein said source of said first drive MISFET is electrically connected to one reference voltage line,
- wherein said source of said second drive MISFET is electrically connected to the other reference voltage line,
- wherein said first and second vertical MISFETs are formed above said reference voltage lines and said first and second drive MISFETs, and
- wherein said first and second vertical MISFETs respectively comprise a source, channel region and drain formed in a laminate extending in a perpendicular direction from said principal surface of said semiconductor substrate, and a gate electrode formed via a gate insulating film on side walls of said laminate.
A semiconductor memory device comprising a memory cell including first and second drive MISFETs and first and second vertical MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first drive MISFET and second drive MISFET being cross-coupled,
- wherein said first and second drive MISFETs are formed in a memory cell-forming region, and peripheral MISFETs are formed in a peripheral circuit-forming region of a principal surface of a semiconductor substrate,
- wherein an interconnection connected to a source region of said first and second drive MISFETs and an interconnection which connects said peripheral MISFETs, are the same interconnection layer, and
- wherein, in said memory cell-forming region, said first and second vertical MISFETs are formed above said first and second drive MISFETs and interconnections.
A method of manufacturing a semiconductor memory device comprising a memory cell including a first and second MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first and second MISFETs being cross-coupled, said method comprising steps of:
- (a) forming first and second MISFETs in a principal surface of a semiconductor substrate;
- (b) forming a first insulating film above said first and second MISFETs;
- and
- (c) forming a first and second connection hole in said first insulating film, electrically connecting said drain of said first MISFET and said gate electrode of said second MISFET through said first connection hole, and electrically connecting said drain of said second MISFET and said gate electrode of said first MISFET through said second connection hole,
- wherein, in step (c), a photolithography step and an etching step of forming said first connection hole, are different from a photolithography step and an etching step of forming said second connection hole.
A method of manufacturing a semiconductor memory device comprising a memory cell including a first and second MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first and second MISFETs being cross-coupled,
- wherein a step of forming gate electrodes of said first and second MISFETs comprises a first step of patterning a conductive film forming said gate electrodes in a first direction of a principal surface of a semiconductor substrate, and a second step of patterning said conductive film in a second direction perpendicular to said first direction.
A method of manufacturing a semiconductor memory device comprising a memory cell including a first and second MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first and second MISFETs being cross-coupled, said method comprising steps of:
- (a) forming first and second MISFETs in a principal surface of a semiconductor substrate;
- (b) forming an oxidation-resistant conductive connection layer via a first insulating film respectively above said first and second MISFETs;
- (c) forming a laminate of a vertical MISFET comprising a source, channel region and drain on said conductive connection layer, which extends in a perpendicular direction to said principal surface of said semiconductor substrate;
- and
- (d) forming a gate insulating film on side walls of said laminate.
A method of manufacturing a semiconductor memory device comprising a memory cell including a first and second MISFETs, and first and second vertical MISFETs, disposed at an intersection of a pair of complementary data lines and a word line, said first MISFET and second MISFET being cross-coupled, in which said first and second vertical MISFETs respectively comprising a source, channel region and drain formed in a laminate which extends in a perpendicular direction to a principal surface of a semiconductor substrate, and a gate electrode formed on side walls of said laminate via a gate insulating film,
- wherein a method for forming said laminate comprises steps of forming a mask layer for etching a film forming said laminate above said film, forming a photoresist pattern above said mask layer, slimming said photoresist pattern, and etching said mask layer using said slimmed photoresist pattern as a mask.
A method of manufacturing a semiconductor memory device comprising a memory cell including a first and second MISFETs, and first and second vertical MISFETs, disposed at an intersection of a pair of complementary data lines and a word line, said first MISFET and second MISFET being cross-coupled, wherein said first and second vertical MISFETs respectively comprise a source, channel region and drain formed in a laminate which extends in a perpendicular direction to a principal surface of a semiconductor substrate, and a gate electrode formed on side walls of said laminate via a gate insulating film, said method comprising steps of:
- (a) forming said first and second MISFETs in a principal surface of a semiconductor substrate;
- (b) forming a first insulating film above said first and second MISFETs;
- (c) depositing a first amorphous silicon film doped with impurities and depositing a second amorphous silicon film of lower concentration than said first amorphous silicon film, above said first insulating film;
- (d) carrying out crystallization by performing a first annealing treatment on said first and second amorphous silicon film;
- (e) after step (d), depositing a third amorphous silicon film doped with impurities to form a laminated film;
- (f) carrying out crystallization by performing a second annealing treatment on said third amorphous silicon film;
- (g) after step (f), forming said laminate by patterning said laminated film.
A method of manufacturing a semiconductor memory device comprising a memory cell including a first and second MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first MISFET and second MISFET being cross-coupled, said method comprising steps of:
- (a) forming said first and second MISFETs on a principal surface of a semiconductor substrate;
- (b) forming a laminate comprising a source, channel region and drain of said first and second vertical MISFETs extending in a perpendicular direction to said principal surface of said semiconductor substrate via a first insulating film respectively over said first and second MISFETs;
- (c) forming an insulating film so as to cover said laminate;
- (d) forming an interconnection groove in said insulating film;
- and
- (e) forming said word line electrically connected to said gate electrodes of said first and second vertical MISFETs by embedding a conductive film in said interconnection groove.
A method of manufacturing a semiconductor memory device comprising a memory cell including a first and second MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first MISFET and second MISFET being cross-coupled, said method comprising steps of:
- (a) forming said first and second MISFETs on a principal surface of a semiconductor substrate;
- (b) forming a laminate comprising a source, channel region and drain of said first and second vertical MISFETs extending in a perpendicular direction to said principal surface of said semiconductor substrate via a first insulating film respectively over said first and second MISFETs;
- and
- (c) forming gate electrodes of said vertical MISFET via gate insulating films on side walls of said laminate in a shape of a side spacer which self-aligns with said side walls of said laminate.
A method of manufacturing a semiconductor memory device comprising a vertical MISFET having a source, channel region and drain formed in a laminate extending perpendicularly to a principal surface of a semiconductor substrate, and having a gate electrode formed via a gate insulating film on side walls of said laminate, said method comprising steps of:
- (a) forming said laminate comprising said source, channel region and drain of said vertical MISFET via a first insulating film on said principal surface of said semiconductor substrate, and extending perpendicularly to said principal surface of said semiconductor substrate;
- and
- (b) forming a gate electrode of said vertical MISFET via said gate insulating film on said side walls of said laminate in a shape of a side spacer which self-aligns with said side walls of said laminate.
A method of manufacturing a semiconductor memory device comprising a vertical MISFET having source, channel region and drain formed in a laminate extending perpendicularly to a principal surface of a semiconductor substrate, and having a gate electrode formed via a gate insulating film on said side walls of said laminate, said method comprising steps of:
- (a) depositing a first amorphous silicon film doped with impurities and, and a second amorphous silicon film of lower concentration than said first amorphous silicon film on said principal surface of said semiconductor substrate;
- (b) performing a first annealing of said first and second amorphous silicon films;
- (c) after step (b), forming a laminated film by depositing a third amorphous silicon film doped with impurities;
- (d) carrying out crystallization by performing a second annealing on said third amorphous silicon film;
- and
- (e) after step (d), forming a laminate by patterning said laminated film.
A method of manufacturing a semiconductor memory device comprising a vertical MISFET having a source, channel region and drain formed in a laminate extending perpendicularly to a principal surface of a semiconductor substrate, and having a gate electrode formed via a gate insulating film on side walls of said laminate,
- wherein said step of forming said laminate comprises steps of forming a mask layer for etching a film forming said laminate above said film, forming a photoresist pattern above said mask layer, slimming said photoresist pattern, and etching said mask layer using said slimmed photoresist pattern as a mask.
A method of manufacturing a semiconductor memory device comprising a memory cell including a first and second MISFETs, and first and second vertical MISFETs, disposed at an intersection of a pair of complementary data lines and a word line, said first MISFET and second MISFET being cross-coupled, wherein said first and second vertical MISFETs respectively comprise a source, channel region and drain formed in a laminate which extends in a perpendicular direction to a principal surface of a semiconductor substrate, and a gate electrode formed on side walls of said laminate via a gate insulating film, said method comprising steps of:
- (a) patterning a thin film formed on conductive film for a gate electrode in a first direction on said principal surface of said semiconductor substrate;
- (b) patterning said thin film in a second direction perpendicular to said first direction;
- and
- (c) patterning said conductive film using thin film patterned in said first and second steps as a mask.
A method of manufacturing a semiconductor memory device comprising a memory cell including a first and second MISFETs, and first and second vertical MISFETs, disposed at an intersection of a pair of complementary data lines and a word line, said first MISFET and second MISFET being cross-coupled,
- wherein said first and second vertical MISFETs respectively comprise a source, channel region and drain formed in a laminate which extends in a perpendicular direction to a principal surface of a semiconductor substrate, and a gate electrode formed on side walls of said laminate via a gate insulating film, and
- wherein said method of forming said gate electrodes of said first and second vertical MISFETs comprises the steps of:
- (a) depositing a first gate electrode conductive film in an amorphous state on said semiconductor substrate;
- (b) depositing a second gate electrode conductive film in a polycrystalline state on said first gate electrode conductive film;
- and
- (c) heat treating said semiconductor substrate to make said first gate electrode conductive film polycrystalline by using said second gate electrode conductive film as a seed crystal.
A method of manufacturing a semiconductor memory device comprising a memory cell including a first and second MISFETs, and first and second vertical MISFETs, disposed at an intersection of a pair of complementary data lines and a word line, said first MISFET and second MISFET being cross-coupled, wherein said first and second vertical MISFETs respectively comprise a source, channel region and drain formed in a laminate which extends in a perpendicular direction to a principal surface of a semiconductor substrate, and a gate electrode formed on side walls of said laminate via a gate insulating film,
- said method comprising a step of simultaneously forming gate electrodes of said first and second vertical MISFETs and said word line by depositing conductive films for gate electrode having a film thickness of more than half a distance between laminates adjoining in said word line extension direction, and less than a distance between laminates adjoining in a direction perpendicular to said word line extension direction.
Dependencies are inferred from the claim text.