Method for fabricating raised source/drain of semiconductor device
AssigneeMacronix International Co., Ltd.
InventorKent Kuohua Chang
Life of this patent
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Abstract
A method for fabricating a raised source/drain of a semiconductor device is described. A gate structure is formed on a substrate, and then a source/drain with a shallow-junction is formed in the substrate beside the gate structure. A spacer is formed on the sidewalls of the gate structure. Thereafter, an elevated layer is formed on the gate structure and the source/drain with a shallow junction, wherein the elevated layer formed on the source/drain serves as an elevated source/drain layer.
Claims30
A method for fabricating a raised source/drain of a semiconductor device, comprising:
- forming a gate structure on a substrate;
- forming a source/drain with a shallow-junction in the substrate beside the gate structure;
- forming a spacer on sidewalls of the gate structure;
- and
- forming an elevated SiGe layer on the gate structure and the source/drain with a shallow junction, wherein the elevated layer formed on the source/drain serves as an elevated source/drain layer.
A method for fabricating a raised source/drain of a semiconductor device, comprising:
- forming a gate structure on a substrate, the gate structure having a capping layer thereon;
- forming a source/drain with a shallow-junction in the substrate beside the gate structure;
- forming a spacer on sidewalls of the gate structure;
- and
- forming an elevated SiGe source/drain layer on the source/drain with a shallow junction.
A method for fabricating a raised source/drain of a semiconductor device, comprising:
- forming a gate structure on a substrate, the gate structure having a capping layer thereon;
- forming a source/drain with a shallow-junction in the substrate beside the gate structure;
- forming a spacer on sidewalls of the gate structure;
- forming an elevated SiGe source/drain layer on the source/drain with a shallow junction;
- removing the capping layer;
- and
- forming a metal silicide layer on the gate structure and the elevated SiGe source/drain layer.
Dependencies are inferred from the claim text.