Method of utilizing fabrication process of poly-si spacer to build flash memory with 2bit/cell

A method utilizing the fabrication process of poly-Si spacers to build a flash memory with 2 bit/cell, comprising the steps of:

• forming a pad oxide and an already defined and patterned silicon nitride layer on a semiconductor substrate;
• performing ion implantation to said substrate to form doped regions with said silicon nitride layer as a mask;
• depositing an oxide on said substrate then planarizing said oxide to remove part of said oxide until said silicon nitride layer is exposed;
• removing said silicon nitride layer, using said oxide to define the region of device, and then removing said pad oxide;
• depositing a tunnel dielectric layer on the surface of said substrate;
• depositing a first poly-Si layer on said substrate to cover said oxide and said tunnel dielectric layer;
• performing anisotropic etch to said first poly-Si layer to form poly-Si spacers at two sides of said oxide;
• and
• depositing an insulating dielectric layer on said substrate and finally forming an already defined second poly-Si layer on said insulating dielectric layer.