Enhanced on-chip decoupling capacitors and method of making same
AssigneeIntel Corporation
InventorsBruce A. Block, Richard Scott List
Life of this patent
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Abstract
An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.
Claims22
An apparatus comprising:
- a capacitor formed between metallization layers on a circuit, the capacitor comprising a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile.
The apparatus of claim 3, wherein the alternating layers of dielectric comprise alternating layers of silicon oxide and silicon nitride.
An apparatus comprising:
- a device structure having a first metal layer:
- an electrically decoupling capacitor stack coupled to the first metal layer having a top electrode wherein the top electrode is coupled through a via a second metal layer superimposed over a portion of the first metal layer;
- and
- an interlayer dielectric layer coupled between the first metal layer and the second metal layer, wherein the interlayer dielectric comprises alternating layers of dissimilar dielectric material defining vertical corrugations in a wall of the via,
- wherein the decoupling capacitor stack conforms to the vertical corrugations.
A method comprising:
- forming an interlayer dielectric comprising alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure;
- forming a via having a corrugated sidewall;
- and
- forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.
A method comprising:
- forming a multilayer interlayer dielectric on an integrated circuit having a metal layer;
- etching a via in the multilayer interlayer dielectric;
- etching corrugations in a surface of the via in the multilayer interlayer dielectric;
- depositing a decoupling capacitor on the surface of the via that conforms to the corrugations in the surface of the via;
- filling the via with a via metal that conforms to the corrugations in the decoupling capacitor;
- and
- forming a metal layer over the via and interlayer dielectric.
Dependencies are inferred from the claim text.