Electrically isolated pillars in active devices
AssigneeMatrix Semiconductor, Inc.
InventorsMichael A. Vyvoda, Manish Bhatia, James M. Cleeves, N. Johan Knall
Life of this patent
Estimating the term…
Abstract
A method of forming an active device is provided. The method includes performing a first patterning operation on a first plurality of layers. This first patterning operation defines a first feature of the active device. Then, a second patterning operation can be performed on at least one layer of the first plurality of layers. This second patterning operation defines a second feature of the active device. Of importance, the first and second patterning operations are performed substantially back-to-back, thereby ensuring that the active device can accurately function.
Claims70
A method of forming an active device, the method comprising:
- performing a first patterning operation on a first plurality of layers, the first patterning operation defining a first feature of the active device;
- and
- performing a second patterning operation on at least one patterned layer of the first plurality of layers, the second patterning operation defining a second feature of the active device, wherein the first and second patterning operations are performed substantially back-to-back.
A method of forming diodes in an array, the method comprising:
- performing a first patterning operation on a first plurality of layers, the first plurality of layers including at least one of a P-type layer and an N-type layer, the first patterning operation forming a first plurality of strips;
- and
- performing a second patterning operation on at least one layer of the first plurality of strips, wherein the first and second patterning operations are performed substantially back-to-back.
An incipient diode structure including vertically formed diodes, the structure comprising:
- a first set of strips including a first terminal and a first portion of a first diode;
- a first pillar including a second portion of the first diode;
- a second set of strips including a common terminal shared by the first diode and a second diode;
- a second pillar including a first portion of the second diode;
- and
- a third set of strips including a second portion of the second diode and another terminal of the second diode, wherein each of the pillars is substantially free of stringers.
A method of forming a pillar from a plurality of layers formed on a wafer, the method comprising:
- performing substantially back-to-back patterning steps,
- wherein a first patterning step etches a plurality of layers in a first direction, thereby forming patterned structures,
- wherein a second patterning step etches the patterned structure in a second direction, and
- wherein the first direction is different from the second direction.
A method of forming an active device, the method comprising:
- performing a first patterning operation on a first plurality of layers, the first patterning operation defining a first terminal of the active device;
- performing a second patterning operation on at least one patterned layer of the first plurality of layers, the second patterning operation defining a first feature of the active device, wherein the first and second patterning operations are performed substantially back-to-back;
- and
- performing a third patterning operation on a second plurality of layers, wherein the third patterning operation defines a second feature and a second terminal of the active device.
A method of forming diodes in an array, the method comprising:
- performing a first patterning operation on a first plurality of layers, the first plurality of layers including a first silicon-type layer, the first patterning operation forming a first plurality of strips;
- and
- performing a second patterning operation on at least one layer of the first plurality of strips, the second patterning operation defining one feature of a plurality of diodes from the first silicon-type layer, wherein the first and second patterning operations are performed substantially back-to-back.
A method of isolating pillars on an integrated circuit, the method including:
- performing a first anisotropic etch on a first plurality of layers, thereby forming patterned structures;
- and
- performing a second anisotropic etch on the patterned structures, thereby forming the functional pillars, wherein the first and second anisotropic etches are performed substantially back-to-back.
A method of forming diodes in an array, the method comprising:
- performing a first patterning operation on a first plurality of layers, the first plurality of layers including an N layer and two P+ layers sandwiching an antifuse layer, the first patterning operation forming a first plurality of strips;
- and
- performing a second patterning operation on at least the N layer of the first plurality of strips, wherein the first and second patterning operations are performed substantially back-to-back.
A monolithic 3-dimensional memory array comprising:
- a first set of strips including a first terminal;
- a second set of strips including a second terminal;
- a third set of strips including a third terminal;
- a first pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said first and second sets of strips, and including a first P doped silicon region, a first N doped silicon region and a first insulating region;
- a second pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said second and third sets of strips, and including a second P doped silicon region, a second N doped silicon region and a second insulating region;
- wherein each of the pillars is substantially free of stringers.
Dependencies are inferred from the claim text.