Method of manufacturing a semiconductor device
AssigneeOki Electric Industry Co., Ltd.
InventorMasashi Takahashi
Life of this patent
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Abstract
This invention relates to a CMOSFET 10 in which a p-type gate electrode 32a and an n-type gate electrode 32b are formed on a silicon substrate 12. The p-type gate electrode 32a comprises, in order, a p-type polycrystalline silicon layer 22a and a tungsten silicide layer 26a. The n-type gate electrode 32b comprises, in order, an n-type polycrystalline silicon layer 22b and a tungsten silicide layer 26b. A carbon-containing polycrystalline silicon layer 24, which is an impurity thermal diffusion prevention layer to suppress the interdiffusion of impurities, is provided between the p-type polycrystalline silicon layer 22a and the tungsten silicide layer 26a.
Claims16
A method of manufacturing a semiconductor device comprising a first gate electrode, having a first impurity diffusion layer of a first conduction type formed in a polycrystalline silicon layer and a high-melting-point metal layer or high-melting-point metal silicide layer, formed in order, and a second gate electrode having a second impurity diffusion layer of a second conduction type formed in said polycrystalline silicon layer and a high-melting-point metal layer or high-melting-point metal silicide layer, formed in order, and positioned at a distance from said first gate electrode;
- wherein said method comprises:
- (a) implanting impurities of the first and the second conduction types respectively into different first and second regions of the polycrystalline silicon layer from above said polycrystalline silicon layer;
- (b) forming, after implanting impurities in the polycrystalline silicon layer, an impurity thermal diffusion prevention layer which prevents diffusion of said impurities implanted into the polycrystalline silicon layer on said polycrystalline silicon layer;
- (c) forming said high-melting-point metal layer or high-melting-point metal silicide layer so as to cover said polycrystalline silicon layer extending from said first region to said second region, to form a compound layer comprising said polycrystalline silicon layer with said impurities implanted, said impurity thermal diffusion prevention layer, and said high-melting-point metal layer or high-melting-point metal silicide layer;
- (d) heat-treating said compound layer, and diffusing said first and second impurities implanted respectively into said first and second regions in said polycrystalline silicon layer, to form said first and second impurity diffusion layers;
- and,
- (e) patterning a layered structure comprising said polycrystalline silicon layer in which are formed said first and second impurity diffusion layers, said impurity thermal diffusion prevention layer, and said high-melting-point metal layer or high-melting-point metal silicide layer, to form said first and second gate electrodes.
A semiconductor device manufacturing method, comprising:
- (a) depositing a polycrystalline silicon layer on a semiconductor substrate;
- (b) implanting p-type impurities into said polycrystalline silicon layer deposited in a region in which a p-type MOS transistor is to be formed on said semiconductor substrate surface, and implanting n-type impurities into said polycrystalline silicon layer deposited in a region in which an n-type MOS transistor is to be formed on said semiconductor substrate surface;
- (c) forming an impurity thermal diffusion prevention layer, which prevents the diffusion of said impurities implanted into the polycrystalline silicon layer, either on said polycrystalline silicon layer deposited in the regions in which said p-type and n-type MOS transistors are to be formed, or, at least, on said polycrystalline silicon layer deposited in the region in which said p-type MOS transistor is to be formed;
- (d) forming after said impurity thermal diffusion prevention layer, forming a high-melting-point metal layer or high-melting-point metal silicide layer so as to cover said polycrystalline silicon layer extending from the region in which said p-type MOS transistor is to be formed, to the region in which said n-type MOS transistor is to be formed;
- (e) heat-treating said polycrystalline silicon layer is subjected, and diffusing said n-type and p-type impurities implanted into said polycrystalline silicon layer in said polycrystalline silicon layer, to form n-type and p-type impurity diffusion layers;
- and,
- (f) patterning, after diffusing said n-type and p-type impurities implanted into said polycrystalline silicon layer, said polycrystalline silicon layer in which are formed said n-type and p-type impurity diffusion layers, said impurity diffusion prevention layer, and said high-melting-point metal layer or high-melting-point metal silicide layer, to form the p-type gate electrode of said p-type MOS transistor and the n-type gate electrode of said n-type MOS transistor.
A semiconductor device manufacturing method, comprising:
- (a) depositing a polycrystalline silicon layer on a semiconductor substrate;
- (b) forming an impurity thermal diffusion prevention layer which prevents the diffusion of said impurities implanted into the polycrystalline silicon layer in a subsequent process, either on said polycrystalline silicon layer deposited in the regions on said semiconductor substrate in which p-type and n-type MOS transistors are to be formed, or, at least on said polycrystalline silicon layer deposited in the region in which said p-type MOS transistor is to be formed;
- (c) implanting p-type impurities in said polycrystalline silicon layer deposited in the region on said semiconductor substrate surface in which the p-type MOS transistor is to be formed, and implanting n-type impurities in said polycrystalline silicon layer deposited in the region on said semiconductor substrate surface in which the n-type MOS transistor is to be formed;
- (d) heat-treating said polycrystalline silicon layer, and diffusing said n-type and p-type impurities implanted into said polycrystalline silicon layer within said polycrystalline silicon layer, to form n-type and p-type impurity diffusion layers;
- (e) forming after implanting p-type impurities in said polycrystalline silicon layer, a high-melting-point metal layer or high-melting-point metal silicide layer so as to cover said polycrystalline silicon layer, extending from the region in which said p-type MOS transistor is to be formed to the region in which said n-type MOS transistor is to be formed;
- and,
- (f) patterning after heat-treating said polycrystalline silicon layer, said polycrystalline silicon layer in which are formed said n-type and p-type impurity diffusion layers, said impurity diffusion prevention layer, and said high-melting-point metal layer or high-melting-point metal silicide layer, to form the p-type gate electrode of said p-type MOS transistor and the n-type gate electrode of said n-type MOS transistor.
Dependencies are inferred from the claim text.