US 2004/0001382 A1 · WRITEBACK AND REFRESH CIRCUITRY FOR DIRECT SENSED DRAM MACRO

Abstract

A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.

Claims20

Dependent claims

A writeback and refresh circuit for a direct sense architecture memory comprising:

a global data line;
a plurality of primary sense amps connected to the global data line and also connected to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines;
a single secondary sense amp connected to the global data line, wherein the secondary sense amp receives data from the primary sense amps over the global data line, and includes a restore/writeback circuit to writeback data over the global data line to a primary sense amp and back into the memory.

Dependencies are inferred from the claim text.

Facts

Application

10/064,306Filed 1 Jul 2002

Published

1 Jan 2004

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 11/40615
Management or control of the refreshing or charge-regeneration cycles: internal triggering or timing of refresh, e.g. hidden refresh, self…
G11C 7/065
Sense amplifiers; Associated circuits , e.g. timing or triggering circuits: differential amplifiers of latching type
G11C 7/1051
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data output circuits, e.g. read-out amplifiers,…
G11C 7/1069
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: i/O lines read…

Writeback and refresh circuitry for direct sensed dram macro

Life of this patent

Writeback and refresh circuitry for direct sensed dram macro

Life of this patent

Abstract

Claims20