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US 2004/0000700 A1Published application
Buried zener diode structure and method of manufacture
AssigneeTexas Instruments Incorporated
InventorsGregory G. Romas JR., Darrel C. Oglesby JR.
Life of this patent
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Abstract
A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.
Claims4
A buried Zener diode comprising:
- a P-type semiconductor substrate having an upper surface;
- an N-type buried layer deposited onto the upper surface of the P-type substrate and driven into the P-type substrate to form an NPN buried collector (DUF) having an exposed upper surface, and defining an exposed upper surface associated with the P-type substrate;
- a P-type implant/deposition (PBL) placed within the DUF and having an exposed upper surface, the PBL defining a diode tank, and further defining the exposed upper surface associated with the DUF;
- an epitaxial (EPI) layer having an upper surface, the EPI layer encasing the exposed upper surface of the P-type substrate, the exposed upper surface of the DUF, and the exposed upper surface of the PBL;
- a field oxide encasing the upper surface of the EPI layer and having two voids between the upper surface of the EPI layer and the diode tank defined by the PBL;
- a P+ deposition (ISO) within each void, and that is driven into the diode tank such that the ISO merges with the PBL;
- an NPN base implant/deposition within each void, and that is driven into the ISO to form a NPN transistor base, the NPN base implant/deposition having an exposed upper surface and a doping concentration significantly higher than that of the ISO;
- an N++ emitter diffusion within a predetermined NPN base implant/deposition and having an exposed upper surface within the associated void, the emitter diffusion extending laterally beyond the NPN transistor base and its associated underlying isolation;
- and
- a contact etch applied to the exposed upper surface of the NPN base implant/deposition and the exposed upper surface of the emitter diffusion, wherein the N++ emitter diffusion and the predetermined NPN base implant/deposition define a N++/P+ Zener diode junction that is removed from the exposed upper surface of the N++ emitter diffusion.
7 more elements
A method of manufacturing a buried Zener diode, the method comprising the steps of:
- providing a P-type semiconductor substrate having an upper surface;
- depositing an N-type buried layer onto the upper surface of the P-type substrate and driving the N-type buried layer into the P-type substrate to form an NPN buried collector (DUF) having an exposed upper surface, and that defines an exposed upper surface associated with the P-type substrate;
- placing a P-type implant/deposition (PBL) within the DUF such that the PBL has an exposed upper surface, the PBL defining a diode tank, and further defining the exposed upper surface associated with the DUF;
- encasing the exposed upper surface of the P-type substrate, the exposed upper surface of the DUF, and the exposed upper surface of the PBL with an epitaxial (EPI) layer having an upper surface;
- encasing the upper surface of the EPI layer with a field oxide;
- creating two voids between the upper surface of the EPI layer and the diode tank defined by the PBL;
- placing a P+ deposition (ISO) within each void, and driving the P+ deposition into the diode tank such that the ISO merges with the PBL;
- placing an NPN base implant/deposition within each void, and driving the NPN base implant/deposition into the ISO to form a NPN transistor base, the NPN base implant/deposition having an exposed upper surface and a doping concentration significantly higher than that of the ISO;
- placing an N++ emitter diffusion encompassing a predetermined NPN base implant/deposition such that the emitter diffusion extends laterally beyond the NPN transistor base and its associated underlying isolation, the emitter diffusion having an exposed upper surface within the associated void;
- and
- applying a contact etch to expose the upper surface of the NPN base implant/deposition and to expose the upper surface of the emitter diffusion, wherein the N++ emitter diffusion and the predetermined NPN base implant/deposition define a N++/P+ Zener diode junction that is removed from the exposed upper surface of the N++ emitter diffusion.
8 more elements
Dependencies are inferred from the claim text.