Dual-bit MONOS/SONOS memory structure with non-continuous floating gate

A dual-bit metal oxide nitride oxide semiconductor (MONOS)/semiconductor oxide nitride oxide semiconductor (SONOS) memory structure with a non-continuous floating gate, said memory structure comprising:

• a semiconductor substrate, wherein a plurality of ion-implanting region therein to respectively use as a source and a drain;
• a tunneling channel dielectric layer positioned overlaying a surface of said semiconductor substrate between said source and said drain;
• at least two floating gates respectively positioned on said tunneling channel dielectric layer, wherein each of said floating gates is composed of a nitride layer and an oxide layer;
• and
• a control gate positioned stacking on a surface of said floating gates and on an exposed surface of said tunneling channel dielectric layer in central region of said two floating gates, wherein said control gate is used to control the channel on or off.