Memory device test system and method

A testing system, comprising:

• a timing generator constructed to generate a first clock signal;
• a frequency multiplier circuit coupled to receive the first clock signal and configured to produce a second clock signal having a frequency greater than a frequency of the first clock signal, and to provide the second clock signal to a memory device;
• a pattern generator coupled to receive the first clock signal and to produce an address signal;
• and
• a waveform shaping circuit operatively coupled to the pattern generator, the waveform shaping circuit being constructed to receive the address signal from the pattern generator and to provide the address signal to the memory device synchronized to the first clock signal.

A method for testing a memory device, comprising:

• providing a clock signal to a memory device such that operations within the memory device are synchronized to the clock signal;
• reading data from the memory device using an address signal synchronized to every x cycles of the clock signal wherein x is greater than 1;
• and
• comparing the data read from the memory device to test data.

A method for testing a memory device, comprising:

• using a first clock signal to produce a second clock signal having a frequency greater than a frequency of the first clock signal;
• providing the second clock signal to the memory device such that operations within the memory device are synchronized to the second clock signal;
• reading data from the memory device using an address signal synchronized to the first clock signal;
• and
• comparing the data retrieved from the memory device during the reading to the test data.

A method for testing a memory device, comprising:

• providing a clock into the memory device;
• inputting an address into the memory device, each address being synchronized with every two cycles of the clock;
• outputting an output data from the memory device according to the address, the output data being synchronized with every cycle of the clock;
• retrieving odd or even, but not both, of the output data;
• and
• comparing the retrieved output data with corresponding even of a standard data.

A method for testing a memory device, comprising:

• generating a first clock signal;
• using the first clock signal to produce a second clock signal having a frequency greater than a frequency of the first clock signal;
• providing the second clock signal to a memory device such that operations within the memory device are synchronized to the second clock signal;
• performing a read and compare operation for each of the even addresses in the address space of the memory device, wherein each read and compare operation comprises (i) providing an address signal to the memory device to retrieve data stored within the memory device at the address wherein the address signal is synchronized to the first clock signal, and (ii) comparing the retrieved data to the test data;
• performing a read and compare operation for each of the odd addresses in the address space of the memory device, wherein each read and compare operation comprises (i) providing an address signal to the memory device to retrieve data stored within the memory device at the address, wherein the address signal is synchronized to the first clock signal, and (ii) comparing the retrieved data to the test data.