US 2003/0229872 A1 · Simulation result verification method and simulation result verification device

Abstract

A simulation result verification method of the present invention compares a simulation result representing the relationship between the time and the output state at a given node, with condition information specifying the conditions for the output state of the given node over time, and evaluates the same. Accordingly, it is possible to determine whether the simulation result and the condition information agree with each other and it is not necessary to visually verify the relationship between the simulation result and the threshold value, thereby shortening the verification time and reducing possible errors in visual verification to a low level.

Claims20

Dependent claims

A simulation result verification method, wherein based on

a simulation result that is obtained by simulating a semiconductor integrated circuit and that represents a relationship between a time and an output state at each of a plurality of nodes of the semiconductor integrated circuit, and
condition information specifying a condition for an output state in a period between times t1 and t2 of one of said nodes,
it is determined whether the output state in the period between the times t1 and t2 of the one node in the simulation results agrees with the output state according to the condition information.

A simulation result verification device wherein, based on

a simulation result that is obtained by simulating a semiconductor integrated circuit and that represents a relationship between a time and an output state at each of a plurality of nodes of the semiconductor integrated circuit, and
condition information specifying a condition for an output state in a period between times t1 and t2 of one of said nodes,
it is determined whether the output state in the period between the times t1 and t2 of the one node in the simulation results agrees with the output state according to the condition information.

Dependencies are inferred from the claim text.

Simulation result verification method and simulation result verification device

Life of this patent

Simulation result verification method and simulation result verification device

Life of this patent

Abstract

Claims20