Electronic design for integrated circuits based process related variations

A method comprising

• generating an electronic design for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit,
• the generating including adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model, and
• using an RC extraction tool in conjunction with generating and adjusting the electronic design.

A method comprising

• generating an electronic design for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit,
• the generating including adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a patter-dependent model, and
• using an RC extraction tool in conjunction with generating and adjusting the electronic design.

A method comprising

• generating an electronic design for an integrated circuit that is to be fabricated in accordance with a design by a process that will impart feature dimension variations to the integrated circuit,
• using a pattern-dependent model to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process.

A method comprising

• using a pattern-dependent model to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process, and
• determining placement attributes for elements of the integrated circuit based on the predicted characteristics.

A method comprising

• using a pattern-dependent model to predict electrical feature geometries of an integrated circuit that is to be fabricated in accordance with a design by a process, the prediction of electrical feature geometries being based on width variations or topographical variations produced by the process.