Method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design

A method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design, comprising:

• storing interconnect polygon information for an integrated circuit design into a dummy polygons layer;
• copying said interconnect polygon information from said dummy polygons layer to a target layer, except for dummy interconnect polygon information;
• and
• performing defect analysis of said integrated circuit design using said target layer instead of said dummy polygons layer.

A method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design, comprising:

• retrieving conductivity layers information for an integrated circuit design from a GDSII formatted file;
• defining a dummy polygons layer and a target layer;
• restoring interconnect polygons from said conductivity layers information into said dummy polygons layer;
• copying said interconnect polygons from said dummy polygons layer to said target layer, except for dummy interconnect polygons;
• and
• performing defect analysis of said integrated circuit design using said target layer.