Method and apparatus for testing a logic cell in a semiconductor device
OwnerWilliam D. Coxinventor
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Abstract
A semiconductor device and method of testing the device having a plurality of logic cells interconnected using vias to connect routing tracks that are disposed among a plurality of layers in the device. The logic cells in the device including at least two three-input look-up tables, one two-input look-up table and a flip-flop. The components in the logic cell are connected so that any look-up table can drive at least one input of any other look-up table and where the flip-flop is connected to the look-up tables so that any look-up table can drive an input of the flip-flop.
Claims26
A semiconductor device comprising:
- a plurality of logic cells interconnected using via connections between routing tracks that are disposed among a plurality of layers, wherein said logic cells comprise:
- at least two three-input look-up tables;
- at least one two-input look-up table;
- a flip-flop;
- and
- wherein the look-up tables are interconnected so that any one look-up table can drive at least one input of at least one other look-up table and the flip-flop is connected to the look-up tables so that any look-up table can drive an input of the flip-flop.
A method of making a semiconductor device, the method comprising:
- forming a semiconductor layer comprising a mask-configurable gate array having logic cells that include at least two three-input look-up tables, at least one two-input look-up table and a flip-flop, wherein the look-up tables are interconnected so that any one look-up table can drive at least one input of at least one other look-up table and the flip-flop is connected to the look-up tables so that any look-up table can drive an input of the flip-flop;
- and
- forming a plurality of metal layers disposed on top of the semiconductor layer for routing connections wherein at least some of the plurality of metal layers configures the gate array logic cells.
A method of testing a programmable logic cell in a semiconductor device, the method comprising:
- selecting at least one component in the logic cell to test;
- sending test data to the at least one component;
- and
- reading the internal nodes of the at least one component using a read circuit in such a manner so as to require a significant charge to flip the state of a read line in the read circuit to indicate that the internal nodes of the at least one component are not floating.
A semiconductor device comprising apparatus for testing a programmable logic cell in the semiconductor device, wherein the apparatus comprises:
- means for selecting at least one component in the logic cell to test;
- means for sending test data to the at least one component;
- and
- means for reading the internal nodes of the at least one component using a read circuit in such a manner so as to require a significant charge to flip the state of a read line in the read circuit to indicate that the internal nodes of the at least one component are not floating.
A semiconductor device according to 22 wherein the look-up table comprises at least one multiplexer.
Dependencies are inferred from the claim text.