Clock control arrangement for a computing system, power management system and processing unit including the same

Clock control arrangement according to any preceding claim including means for detecting an increase of the temperature of the processing unit, and means for forcing the switching back to said first clock in response to said detection of increase of the temperature.

Clock control arrangement according to any preceding claim including a watchdog mechanism for switching back to said first clock after the expiration of a predetermined period.

Clock control arrangement according to any preceding claim including a Phase Locked Loop (PLL) producing a set of different frequencies which are used for driving the processor in accordance with the activity monitored on the processor bus.

Clock control arrangement according to any preceding claim adapted to control the clocking of a processor or the processing unit of a video card.

Power management system for a computing system including a processing unit, such as a processor, and a clocking arrangement generating at least a first clock having a first frequency and a second clock having a second higher frequency, said clocking arrangement comprising:

• means for monitoring the activity of said processing unit;
• means for switching the clocking of said processor to said first clock in response to a low level of activity of said processing unit.

Semiconductor chip comprising a processing unit operational at least at a first and a second clock frequency, the frequency of said second clock being at a higher value than the frequency of said first clock, said chip further including:

• means (510, 530) for monitoring a state of high activity of said processing unit;
• means (550) for deriving from said monitoring a control signal requesting said first or said second clock frequency.