US 2003/0229815 A1 · Clock generation system

Abstract

A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S/N ratios in spite of the SIN ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.

Claims17

Dependent claims

A clock generation system for generating at least a first-frequency clock having a first frequency, a second-frequency clock having a second frequency, and a third-frequency clock having a third frequency, said clock generation system comprising:

a first PLL circuit supplied with said first-frequency clock as a reference clock and adapted to generate an intermediate-frequency clock having an intermediate frequency having a predetermined first ratio to said reference frequency;
a second PLL circuit supplied with said intermediate-frequency clock and adapted to generate said second-frequency clock, with said second frequency having a predetermined second ratio to said intermediate frequency;
and
a third PLL circuit supplied with said intermediate-frequency clock and adapted to generate said third-frequency clock, with said third frequency having a predetermined third ratio to said intermediate frequency.

1 more element

a first PLL circuit supplied with a reference clock and adapted to generate said first-frequency clock, with said first frequency having a predetermined first ratio to the frequency of said reference clock;
a second PLL circuit supplied with said reference clock and adapted to generate said second-frequency clock, with said second frequency having a predetermined second ratio to the frequency of said reference clock;
and
a third PLL circuit supplied with said reference clock and adapted to generate said third-frequency clock, with said third frequency having a predetermined third ratio to the frequency of said reference clock.

1 more element

A clock generation system for generating at least a first-frequency clock having a first frequency, a second-frequency clock having a second frequency, a third-frequency clock having a third frequency, and a fourth-frequency clock having a frequency that double of said first frequency, said clock generation system comprising:

a first PLL circuit supplied with said first-frequency clock as a reference clock and adapted to generate an intermediate-frequency clock having an intermediate frequency having a predetermined first ratio to said reference frequency;
a frequency divider for generating said fourth-frequency clock by frequency-dividing the output of said first PLL circuit by a predetermined factor;
a second PLL circuit supplied with said intermediate-frequency clock and adapted to generate said second-frequency clock, with said second frequency having a predetermined second ratio to said intermediate frequency;
and
a third PLL circuit supplied with said intermediate-frequency clock and adapted to generate said third-frequency clock, with said third frequency having a predetermined third ratio to said intermediate frequency.

2 more elements

Dependencies are inferred from the claim text.

Clock generation system

Life of this patent

Clock generation system

Life of this patent

Abstract

Claims17