Controller interface
AssigneeDactron
InventorsJames Zhuge, Zhengge Tang
Life of this patent
Estimating the term…
Abstract
An interface includes a slave digital signal processor (DSP) and a master DSP connected to the slave DSP through a communications port. The master DSP includes a memory; and a direct memory access (DMA) to the memory. A field programmable gate array (FPGA) is connected to the master DSP. The FPGA includes a dual port random access memory (RAM) in communication with the DMA. A universal serial bus (USB) interface is connected to the FPGA through the dual port RAM.
Claims20
An apparatus for providing a communications interface, the apparatus comprising:
- a master processor having:
- a memory, and
- a direct memory access (DMA) to said memory;
- control logic in communication with said master processor, said control logic comprising a dual port random access memory (RAM) in communication with said DMA;
- and
- a communications interface in communication with said control logic through said dual port RAM.
The apparatus as recited in clam 1 wherein said slave processor is a slave digital signal processor.
A method for transmitting data through a communications interface, the method comprising the steps of:
- storing data in a memory of a master processor, said memory having a direct memory access (DMA);
- transmitting data from the memory of the master processor to a dual-port random access memory (RAM) in a control logic circuit through the DMA;
- and
- transmitting data from the dual-port RAM to a communications interface.
A system for transmitting data through a communications interface, the system comprising:
- means for storing data in a memory of a master processor, said memory having a direct memory access (DMA);
- means for transmitting data from the memory of the master processor to a dual-port random access memory (RAM) in a control logic circuit through the DMA;
- and
- means for transmitting data from the dual-port RAM to a communications interface.
An interface comprising:
- a slave digital signal processor (DSP);
- a master DSP connected to said slave DSP through a communications port, said master DSP comprising:
- a memory;
- and
- a direct memory access (DMA) to said memory;
- a field programmable gate array (FPGA) connected to said master DSP, said FPGA comprising a dual port random access memory (RAM) in communication with said DMA;
- and
- a universal serial bus (USB) interface connected to said FPGA through said dual port RAM.
Dependencies are inferred from the claim text.