US 2003/0228737 A1 · Method of fabricating a drain isolated LDMOS device

Abstract

A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are defined in a P-epi layer surrounded by a buried NBL region (14) connected with a deep low resistance drain region (16) forming a guardring. This additional laterally extending p-doped region (56,62,72) reduces minority carrier build up such that recovery time is significantly reduced, and power loss is also significantly reduced due to reduced collection time of the minority carriers. The device may be formed as an LDMOS device.

Claims16

Dependent claims

A method of reducing minority carrier lifetime in a transistor, comprising the steps of:

a) forming the transistor utilizing a P-epi layer defined upon a n-type buried layer, the transistor including a first p-type region defined in the P-epi layer proximate a source and having a higher p-type dopant concentration than the P-epi layer, further including a second p-type region defined proximate the first p-type region in the P-epi layer;
and
b) defining an n-type guardring about the P-epi layer and the first and second p-type regions to contain the minority carriers.

Dependencies are inferred from the claim text.

Facts

Application

10/167,283Filed 11 Jun 2002

Published

11 Dec 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 10/30
Isolation regions in semiconductor bodies between components of integrated devices: isolation regions comprising PN junctions
H10D 30/603
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having asymmetry in the channel direction, e.g. lateral…
H10D 62/371
Of igfets: inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
H10W 10/031
Manufacture or treatment: of isolation regions comprising PN junctions

Method of fabricating a drain isolated LDMOS device

Life of this patent

Method of fabricating a drain isolated LDMOS device

Life of this patent

Abstract

Claims16