Cam cell

A content addressable memory circuit in a semiconductor substrate comprising:

• a match signal output having a logical state set to a first value;
• a compare circuit for comparing a stored data value to an input compare data value having an enable input, a match output coupled to the match signal output, a compare data input coupled to a compare data signal, and a stored data input, wherein if the enable input receives an enable true signal and the stored data input receives a stored data signal and the compare data input receives a compare data signal then the logical state of the match signal output will change to a second value thereby indicating a no match;
• a first data storage device for storing a data value having first and second word lines, first and second bit lines, a stored data output, and a first conductive strip electrically coupling the stored data output to the stored data input of the compare circuit wherein the first word line of the first data storage device is formed in a first conductive region and the second word line of the first data storage device is formed physically separate and distinct from the first conductive region in a second conductive region;
• and
• a second data storage device for storing an enable value having first and second word lines, first and second bit lines, an enable output, and a second conductive strip electrically coupling the enable output to the enable input of the compare circuit wherein the first word line of the second data storage device is formed in a third conductive region and the second word line of the second data storage device is formed physically separate and distinct from the third conductive region in a fourth conductive region.

A content addressable memory circuit comprising:

• a first and second memory circuits, each memory circuit having a first and second pull-down transistor, a first and second pull-up transistor, and a first and second pass transistor, each transistor having a gate, a source region and a drain region;
• a compare circuit having a first and second compare transistor, a first and second enable transistor, and a data-true and data-false transistor, each transistor having a gate, a source region and a drain region;
• the gate of the first pull-down transistor of the first memory circuit being electrically coupled to the gate of the first pull-up transistor of the first memory circuit, to the drain region of a second pull-down transistor of the first memory circuit, to the drain region of a second pull-up transistor of the first memory circuit, to the drain region of a second pass transistor of the first memory circuit, and to the gate of the data-true transistor of the compare circuit;
• the gate of the second pull-down transistor of the first memory circuit being electrically coupled to the gate of the second pull-up transistor of the first memory circuit, to the drain region of the first pull-down transistor of the first memory circuit, to the drain region of the first pull-up transistor of the first memory circuit, to the drain region of the first pass transistor of the first memory circuit, and to the gate of the data-false transistor of the compare circuit;
• the gate of the second pull-down transistor of the second memory circuit being electrically coupled to the gate of the second pull-up transistor of the second memory circuit, to the drain region of the first pull-down transistor of the second memory circuit, to the drain region of the first pull-up transistor of the second memory circuit, and to the drain region of the first pass transistor of the second memory circuit;
• the gate of the first pull-down transistor of the second memory circuit being electrically coupled to the gate of the first pull-up transistor of the second memory circuit, to the drain region of the second pull-down transistor of the second memory circuit, to the drain region of the second pull-up transistor of the second memory circuit, to the drain region of the second pass transistor of the second memory circuit, and to the gates of the first and second enable transistors of the compare circuit;
• the first compare transistor having the gate electrically coupled to a first compare signal, the source region electrically coupled to the drain region of the first enable transistor, and the drain region electrically coupled to a match signal;
• the second compare transistor having the gate electrically coupled to a second compare signal, the source region electrically coupled to the drain region of the second enable transistor, and the drain region electrically coupled to the match signal;
• the first enable transistor having the source region electrically coupled to the drain region of the data-true transistor;
• the second enable transistor having the source region electrically coupled to the drain region of the data-false transistor;
• the first pass transistor of the first memory circuit having the gate electrically coupled to a first word line signal, and the source region electrically coupled to a first bit line signal;
• the second pass transistor of the first memory circuit having the gate electrically coupled to the first word line signal, and the source region electrically coupled to a second bit line signal;
• the first pass transistor of the second memory circuit having the gate electrically coupled to the second word line signal, and the source region electrically coupled to the first bit line signal;
• the second pass transistor of the second memory circuit having the gate electrically coupled to the second word line signal, and the source region electrically coupled to the second bit line signal;
• a first supply electrically coupled to the source region of first and second pull-down transistors of the first memory circuit, to the source region of the first and second pull-down transistors of the second memory circuit, to the source region of the data-true transistor, and to the source region of the data-false transistor;
• and
• a second supply electrically coupled to the source regions of the first and second pull-up transistors of the first memory circuit, and to the source regions of the first and second pull-up transistors of the second memory circuit.

A method of operating a content addressable memory circuit comprising:

• storing a first data in the device;
• storing an enable value in the device;
• providing the data value to a compare circuit of the device;
• providing the enable value to a compare circuit of the device;
• applying compare data to the compare circuit of the device;
• comparing the first data to the compare data;
• and
• outputting an indication if a match was obtained between the first data and the compare data.