Stabilization technique for phase-locked frequency synthesizers
AssigneeThe Regents of the University of California
InventorsTai-Cheng Lee, Behzad Razavi
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Abstract
A stabilization technique that relaxes the tradeoff between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use of a discrete-time delay element, thereby obviating the need for resistors in the loop filter.
Claims25
A phase-locked frequency synthesizer, comprising:
- a phase-frequency detector (PFD) for comparing a phase of a reference signal with a phase of a feedback signal and generating Up and Down signals, depending on whether the phase of the reference signal leads or lags the phase of the feedback signal;
- first and second charge pumps (CPs) for generating positive and negative charge pulses in response to the Up and Down signals from the phase-frequency detector;
- a delay element for delaying the positive and negative charge pulses from the second charge pump;
- a loop filter for integrating the positive and negative charge pulses from the first charge pump and the delayed positive and negative charge pulses from the second charge pump, and for generating a control voltage in response thereto;
- a voltage-controlled oscillator (VCO) for accepting the control voltage from the loop filter and for changing a frequency of an output of the VCO in response thereto;
- and
- a divider for dividing the output of the VCO and generating the feedback signal therefrom.
A phase-locked frequency synthesizer including a delay element for delaying positive and negative charge pulses from a charge pump, wherein the delay element introduces a zero in a open-loop transfer function of the phase-locked frequency synthesizer.
A phase-locked frequency synthesizer, comprising:
- N charge pumps (CPs) for generating positive and negative charge pulses in response to Up and Down signals received from a phase-frequency detector;
- and
- N−1 delay elements for delaying the positive and negative charge pulses from N−1 of the charge pumps;
- wherein the positive and negative charge pulses from a first one of the N charge pumps and the delayed positive and negative charge pulses from the N−1 of the charge pumps are integrated in order to generate a control voltage for a voltage-controlled oscillator (VCO) in response thereto.
A method for operating a phase-locked frequency synthesizer, comprising:
- generating positive and negative charge pulses in N charge pumps (CPs) in response to Up and Down signals received from a phase-frequency detector;
- and
- delaying the positive and negative charge pulses from N−1 of the charge pumps in N−1 delay elements;
- wherein the positive and negative charge pulses from a first one of the N charge pumps and the delayed positive and negative charge pulses from the N−1 of the charge pumps are integrated in order to generate a control voltage for a voltage-controlled oscillator (VCO) in response thereto.
Dependencies are inferred from the claim text.