Fast, stable overload recovery circuit and method

A differential input circuit comprising:

• (a) an input stage receiving an input signal and having first and second output terminals;
• (b) an output stage including a pull-up transistor having a source coupled to a first supply voltage, a gate coupled to the first output terminal, and a drain coupled to an output conductor conducting an output signal, and a pull-down transistor having a source coupled to a second supply voltage, a gate coupled to the second output terminal, and a drain coupled to the output conductor;
• and
• (c) a first overload recovery circuit coupled between the output conductor and the gate of the pull-up transistor for limiting a voltage on the gate of the pull-up transistor in response to the output voltage when the output voltage is within a first predetermined range of the first supply voltage, wherein the first overload recovery circuit includes a pull-up recovery transistor having a source coupled to the output conductor and a drain coupled to the gate of the pull-up transistor, the first overload recovery circuit including a first common-gate amplifier having an inverting input coupled to the output conductor, a non-inverting input coupled to the first supply voltage, and an output coupled to a gate of the pull-up recovery transistor, the first common-gate amplifier having a built-in offset voltage that exceeds a first predetermined value.

A method of operating a differential input circuit including:

• (a) applying an input signal to an input stage;
• (b) providing an output stage including a pull-up transistor having a source coupled to a first supply voltage, a gate coupled to a first output terminal of the input stage, and a drain coupled to an output conductor conducting an output voltage, and a pull-down transistor having a source coupled to a second supply voltage, a gate coupled to a second output terminal of the input stage, and a drain coupled to the output conductor;
• and
• (c) reducing the amount of time required for the differential input circuit to recover from an overload condition by providing a pull-up recovery transistor having a source coupled to the output conductor and a drain coupled to the gate of the pull-up transistor and by providing an amplifier having an inverting input coupled to the output conductor, a non-inverting input coupled to the first supply voltage, and an output coupled to a gate of the pull-up recovery transistor, the amplifier having a built-in offset voltage that exceeds a predetermined value, in order to limit the voltage on the gate of the pull-up transistor in response to the output voltage when the output voltage is within a predetermined range from the first supply voltage.

A method of operating a differential input circuit including:

• (a) applying an input signal to an input stage;
• (b) providing an output stage including an output transistor having a source coupled to a supply voltage, a gate coupled to an output terminal of the input stage, and a drain coupled to an output conductor conducting an output voltage;
• and
• (c) reducing the amount of time required for the differential input circuit to recover from an overload condition by providing a recovery transistor having a source coupled to the output conductor and a drain coupled to the gate of the output transistor and by providing an amplifier having a first input coupled to the output conductor, a second input coupled to the supply voltage, and an output coupled to a gate of the recovery transistor, the amplifier having a built-in offset voltage that exceeds a predetermined value, in order to limit the voltage on the gate of the output transistor in response to the output voltage when the output voltage is within a predetermined range from the supply voltage.

A differential input circuit comprising:

• (a) an input stage receiving an input signal and having first and second output terminals;
• (b) an output stage including a pull-up transistor having a source coupled to a first supply voltage, a gate coupled to the first output terminal, and a drain coupled to an output conductor conducting an output signal, a pull-down transistor having a source coupled to a second supply voltage, a gate coupled to the second output terminal, and a drain coupled to the output conductor;
• and
• (c) a first overload recovery circuit coupled between the output conductor and the gate of the pull-up transistor for limiting a voltage on the gate of the pull-up transistor in response to the output voltage when the output voltage is within a first predetermined range of the first supply voltage, wherein the first overload recovery circuit includes a pull-up recovery transistor having a source coupled to the first supply voltage and a drain coupled to the gate of the pull-up transistor, the first overload recovery circuit including a first amplifier having an inverting input coupled to the output conductor, a non-inverting input coupled to the first supply voltage, and an output coupled to a gate of the pull-up recovery transistor, the first amplifier having a built-in offset voltage that exceeds a first predetermined value.

A differential input circuit comprising:

• (a) an input stage receiving an input signal and having an output terminal;
• (b) an output stage including an output transistor having a source coupled to a supply voltage, a gate coupled to the output terminal, and a drain coupled to an output conductor conducting an output signal;
• and
• (c) an overload recovery circuit coupled between the output conductor and the gate of the output transistor for limiting a voltage on the gate of the output transistor in response to the output voltage when the output voltage is within a predetermined range of the supply voltage, wherein the overload recovery circuit includes a recovery transistor having a source coupled to the supply voltage and a drain coupled to the gate of the output transistor, the overload recovery circuit including an amplifier having a first input coupled to the output conductor, a second input coupled to the supply voltage, and an output coupled to a gate of the recovery transistor, the amplifier having a built-in offset voltage that exceeds a predetermined value.