Level shifting circuit
AssigneeAu Optronics Corporation
InventorJian-Shen Yu
Life of this patent
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Abstract
A level shifting circuit. The gate of the PMOS transistor is coupled to an input terminal, and the source of the PMOS transistor is coupled to a power source. The drain of the NMOS transistor is coupled to the drain of the PMOS transistor. The source of the NMOS transistor is coupled to a reverse input terminal. The gate of the NMOS transistor is coupled to the power source. The reverse logic gate having a first terminal is coupled to the drain of the NMOS transistor and a second terminal is coupled to the output terminal.
Claims13
A level shifting circuit, comprising:
- a first PMOS transistor having a first drain, a first gate coupled to an input terminal and a first source coupled to a power source;
- a first NMOS transistor having a second drain coupled to the first drain, a second source coupled to a reverse input terminal and a second gate coupled to the power source;
- and
- a reverse logic gate having a first terminal coupled to the first drain and a second terminal coupled to a output terminal.
A level shifting circuit, comprising:
- a first PMOS transistor having a first drain, a first gate coupled to an input terminal and a first source coupled to a power source;
- a first NMOS transistor having a second drain coupled to the first drain, a second source coupled to a reverse input terminal and a second gate coupled to the power source;
- a second PMOS transistor having a third gate coupled to the first drain, a third drain coupled to an output terminal and a third source coupled to the power source;
- and
- a second NMOS transistor having a fourth gate coupled to the second gate, a fourth drain coupled to the output terminal and a fourth source coupled to the input terminal.
A level shifting circuit, comprising:
- a first PMOS transistor having a first drain, a first gate coupled to an input terminal and a first source coupled to a power source;
- a voltage difference element having a first terminal coupled to the first drain, and a second terminal;
- a second PMOS transistor having a second source coupled to the power source, a second gate coupled to the second terminal and a second drain coupled to an output terminal;
- a first NMOS transistor having a third drain coupled to the second gate, a third gate coupled to the first drain and a third source coupled to a reverse input terminal;
- and
- a second NMOS transistor having a fourth source coupled to the input terminal, a fourth drain coupled to the output terminal and a fourth gate coupled to the first drain.
A level shifting circuit, comprising:
- a first PMOS transistor having a first drain, a first source coupled to a first power source and a first gate coupled to a second power source;
- a voltage difference element having a first terminal coupled to the first drain, and a second terminal;
- a second PMOS transistor having a second source coupled to the first power source, a second gate coupled to the second terminal and a second drain coupled to an output terminal;
- a first NMOS transistor having a third drain coupled to the second gate, a third gate coupled to the first drain and a third source coupled to a reverse input terminal;
- and
- a second NMOS transistor having a fourth source coupled to the input terminal, a fourth drain coupled to the output terminal and a fourth gate coupled to the first drain.
Dependencies are inferred from the claim text.