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US 2003/0227300 A1Published application
Multiple asynchronous switching system
AssigneeVIA-Cyrix, Inc.
InventorWilliam V. Miller
Life of this patent
Estimating the term…
Abstract
A system for allowing an asynchronous clock signal to be selected from a plurality of asynchronous clock signals without causing glitches. In the system, a requestor is connected to control signals. The control signals indicate to the requestor which asynchronous clock signal, of the two or more clock signals, to request. The requestor informs a selector of the request. The selector determines which asynchronous clock signal was selected. The selected asynchronous clock is then detected by the detector. The detector feeds the selected asynchronous clock signal to a signal output. The signal output releases the selected asynchronous clock signal.
Claims21
An asynchronous clock switching system comprising:
- two or more asynchronous clock signals;
- a requestor, coupled to a detector, for requesting an asynchronous clock signal from the two or more asynchronous clock signals;
- selection signals, including a delay, coupled to the detector, which selects an asynchronous clock signal from the two or more asynchronous clock signals;
- the detector, coupled to a signal output, which detects the selected asynchronous clock signal;
- and
- the signal output, coupled to the detector and the requestor, which outputs the selected asynchronous clock signal.
3 more elements
An asynchronous clock switching system comprising:
- a requestor;
- one or more control signals input into the requestor;
- one or more request signals output from the requestor;
- one or more second detector logic gates for receiving respective of the one or more request signals;
- one or more state machines for receiving input from the respective of the one or more second detector logic gates;
- one or more selection signals associated with the respective one or more state machines, coupled to buffers, output from the one or more state machines;
- one or more first detector logic gates associated with the respective one or more state machines for receiving one or more selection signals not associated with the respective one or more state machines and outputting to the second detector logic gates;
- one or more third detector logic gates associated with the respective one or more state machines for receiving the respective one or more selection signals;
- two or more asynchronous clock signals coupled to an input of the respective one or more third detector logic gate;
- a signal output receiving an input from the one or more third detector logic gates and providing an output to the requestor;
- and
- one or more inverters associated with the respective one or more state machines for receiving the respective two or more asynchronous clock signals and outputting to the respective one or more state machines.
9 more elements
An asynchronous clock switching system comprising:
- a requestor;
- one or more control signals input into the requestor;
- one or more request signals output from the requestor;
- one or more second detector logic gates for receiving respective of the one or more request signals;
- one or more state machines for receiving input from the respective of the one or more second detector logic gates;
- one or more selection signals associated with the respective one or more state machines, coupled to buffers, output from the one or more state machines;
- one or more first detector logic gates associated with the respective one or more state machines for receiving one or more selection signals not associated with the respective one or more state machines and outputting to the second detector logic gates;
- one or more third detector logic gates associated with the respective one or more state machines for receiving the respective one or more selection signals;
- two or more asynchronous clock signals coupled to an input of the respective one or more third detector logic gate and to the one or more respective state machines;
- and
- a signal output receiving an input from the one or more third detector logic gates and providing an output to the requestor.
8 more elements
An asynchronous clock switching system comprising:
- a requestor;
- one control signal input into the requestor;
- outputs from the requestor comprise two request signals;
- two first detector logic gates for receiving the two respective request signals as inputs;
- two state machines for receiving inputs from the two respective first detector logic gates;
- two selection signals output from the two respective state machines;
- two detector inverters for receiving the respective non-associated selection signals as inputs and providing output into the respective two first detector logic gates;
- two second detector logic gates for receiving the respective two selection signals;
- two asynchronous clock signals input into the respective two second detector logic gates;
- two inverters for receiving the respective two asynchronous clock signals and providing output to the two respective state machines;
- a signal output receiving inputs from the two second detector logic gates;
- and the signal output coupled to the requestor.
9 more elements
Dependencies are inferred from the claim text.