Method and apparatus for regulating the efficiency of a power supply in a computer system
AssigneeIntel Corporation
InventorDon J. Nguyen
Life of this patent
Estimating the term…
Abstract
A computer system having multiple components capable of being in either a wake or sleep state includes a power manager and a voltage regulator. The power manager may generate a power state status signal indicating the power states of the components, and this signal may be provided to the voltage regulator. In response, the voltage regulator may operate in a synchronous mode when the power state status signal indicates that the components are in a wake state. The voltage regulator may operate in a non-synchronous mode when the power state status signal indicates that the components are in a sleep state.
Claims28
A computer system comprising:
- a power manager to generate a power state status signal to indicate a power state of a plurality of components of the computer system;
- and
- a voltage regulator to supply a voltage to the plurality of components and to transition between synchronous and non-synchronous modes of operation when the plurality of components transitions between first and second power states, as indicated by the power state status signal.
A voltage regulator comprising:
- an input to receive a power state status signal to indicate power states of first and second components of a computer system;
- an output to supply a voltage to the first and second components at a voltage level;
- a pull-up power transistor to raise the voltage level;
- and
- a pull-down power transistor to lower the voltage level, the pull-down power transistor to operate synchronously with the pull-up power transistor when the power state status signal indicates that the first and second components are in wake states, and to operate non-synchronously with the pull-up power transistor when the power state status signal indicates that the first and second components are in sleep states.
A voltage regulator comprising:
- an input to receive a power state status signal to indicate power states of first and second components of a computer system;
- an output to supply a voltage to the first and second components at a voltage level;
- a pull-up power transistor to raise the voltage level;
- and
- first and second pull-down power transistors to lower the voltage level, the first pull-down power transistor to be off when the power state status signal indicates that the first and second components are in sleep states.
A method comprising:
- coupling a voltage regulator to a plurality of components of a computer system to supply a voltage to the plurality of components;
- coupling the plurality of components to a power manager to indicate a power state of the plurality of components;
- and
- coupling the power manager to the voltage regulator to provide a power state status signal to indicate the power state of the plurality of components.
Dependencies are inferred from the claim text.