Flexible routing channels among vias
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCliff Hou, Lee-Chung Lu, Chia-Lin Cheng
Life of this patent
Estimating the term…
Abstract
Flexible routing channels among vias is disclosed. A semiconductor device of one embodiment includes a number of metal layers, a number of dielectric layers, a number of via holes, and a number of routing channels. The metal layers are organized along a vertical axis. The dielectric layers are alternatively positioned relative to the metal layers. The via holes are situated within the dielectric layers and electrically connect a lower layer of the metal layers to an upper layer of the metal layers. The routing channels are situated within the metal layers and provide for electrical routing through the device along at least one of two horizontal axes of a horizontal plane perpendicular to the vertical axis.
Claims20
A semiconductor device comprising:
- a plurality of metal layers organized along a vertical axis;
- a plurality of dielectric layers alternatively positioned relative to the plurality of metal layers;
- a plurality of via holes situated within the plurality of dielectric layers to electrically connect a lower layer of the plurality of metal layers to an upper layer of the plurality of metal layers;
- and,
- a plurality of routing channels situated within the plurality of metal layers to provide for electrical routing through the semiconductor device along a horizontal plane perpendicular to the vertical axis.
A layout for a semiconductor integrated circuit (IC) comprising:
- a layout portion specifying a plurality of metal layers organized along a vertical axis;
- a layout portion specifying a plurality of dielectric layers alternatively positioned relative to the plurality of metal layers;
- a layout portion specifying a plurality of via holes situated within the plurality of dielectric layers to electrically connect a lower layer of the plurality of metal layers to an upper layer of the plurality of metal layers;
- and,
- a layout portion specifying a plurality of routing channels situated within the plurality of metal layers to provide for electrical routing through the semiconductor IC along a horizontal plane perpendicular to the vertical axis.
A method comprising:
- estimating an average current and a peak current for a layout of a semiconductor integrated circuit (IC) comprising:
- a layout portion specifying a plurality of metal layers organized along a vertical axis;
- a layout portion specifying a plurality of dielectric layers alternatively positioned relative to the plurality of metal layers;
- a layout portion specifying a plurality of via holes situated within the plurality of dielectric layers to electrically connect a lower layer of the plurality of metal layers to an upper layer of the plurality of metal layers;
- and,
- a layout portion specifying a plurality of routing channels situated within the plurality of metal layers to provide for electrical routing through the semiconductor IC along a horizontal plane perpendicular to the vertical axis;
- determining a number of the plurality of vias as needed based on the average current and the peak current determined;
- and,
- providing the number of the plurality of vias needed as electrically connected to one another.
Dependencies are inferred from the claim text.