Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby

An array of electrically programmable and erasable memory devices comprising:

• a substrate of semiconductor material having a first conductivity type and a surface;
• spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
• each of the active regions including a plurality of memory cells, each of the memory cells comprising:
• first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having first and second portions,
• an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region, and
• an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion.

A method of forming a semiconductor memory cell, comprising the steps of:

• forming first and second spaced-apart regions in a semiconductor substrate, with a channel region defined in the substrate therebetween having a first portion and a second portion, wherein the substrate has a first conductivity type and a surface, and the first and second regions have a second conductivity type;
• forming an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion is formed to extend along and be insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region;
• and
• forming an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion.

A method of forming an array of semiconductor memory cells, comprising the steps of:

• forming a plurality of first and second spaced-apart regions of a second conductivity type in a semiconductor substrate of a first conductivity type, with a plurality of channel regions each defined in the substrate between one of the first regions and one of the second regions, wherein each channel region includes a first portion and a second portion, and wherein the substrate has a surface;
• forming a plurality of electrically conductive floating gates each having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein each of the floating gate first portions is formed to extend along and be insulated from one of the channel region second portions for controlling a conductivity of the one channel region second portion, and wherein each of the floating gate second portions is positioned for capacitive coupling with one of the first regions;
• and
• forming a plurality of electrically conductive control gates each disposed adjacent to and insulated from one of the channel region first portions for controlling a conductivity of the one channel region first portion.