System and method for preventing memory access errors

A system for preventing memory access errors, comprising:

• a memory chip having a plurality of memory locations;
• a memory controller configured to transmit a memory address for identifying one of the memory locations of the memory chip;
• and
• logic external to the memory chip, the logic configured to receive a signal indicative of whether the memory address is associated with a detected parity error, the logic further configured to prevent the memory chip from accessing the memory locations based on the memory address if the signal indicates that the memory address is associated with a detected parity error.

A method for preventing memory access errors, comprising:

• communicating a memory address for identifying one of a plurality of memory locations within a memory chip;
• receiving, external to the memory chip, a signal indicative of whether the memory address is associated with a detected parity error;
• analyzing, external to the memory chip, the signal received in the receiving step;
• and
• disabling, based on the analyzing step, the memory chip from utilizing the memory address to access the memory locations.

A method for preventing memory access errors, comprising:

• transmitting a memory address to a memory chip, the memory address comprising chip select information;
• receiving a signal indicative of whether the memory address is associated with a parity error;
• adjusting the chip select information based on the received signal;
• and
• controlling, based on the chip select information, whether the memory chip performs a memory access in response to the memory address.