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US 2003/0226079 A1Published application
Scan-path flip-flop circuit for integrated circuit memory
AssigneeNEC Electronics Corporation
InventorKoji Kanba
Life of this patent
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AssigneeNEC Electronics Corporation
InventorKoji Kanba
Estimating the term…
A scan-path flip-flop circuit for an integrated circuit memory comprises a number of successively arranged flip-flops. Each flip-flop comprises a master latching circuit for latching a first signal supplied from an associated input terminal of the integrated circuit memory in response to a normal-mode clock signal, supplying the latched first signal to the integrated circuit memory, and further latching a second signal in response to a first scan-mode clock signal. The first signal from the master latching circuit is latched in a slave latching circuit in response to the normal-mode clock signal, and the second signal from the master latching circuit is latched in the slave latching circuit in response to a second scan-mode clock signal. The slave latching circuit of each preceding flip-flop is connected to the master latching circuit of a succeeding flip-flop for shifting the second signal in response to the first scan-mode clock signal.
A test circuit for an integrated circuit memory, comprising a scan-path flip-flop circuit capable of performing a latching operation, said scan-path flip-flop circuit being connected to a plurality of input terminals of the integrated circuit memory for producing a plurality of latched signals in response to input signals applied to said input terminals and applying the latched signals to the integrated circuit memory.
A scan-path flip-flop circuit for an integrated circuit memory, comprising:
Dependencies are inferred from the claim text.