US 2003/0226076 A1 · PC and ATE integrated chip test equipment

Abstract

The present invention relates to a test equipment of a chip memory device. A memory pattern test is implemented using a pattern generation substrate in which a processor is designed in an EPLD for thereby implementing a PC test and pattern programming, so that a test evaluated under a PC environment formed of a CPU and chip sets. Two processes of a chip device test and automatic test are performed in one equipment using a generated test pattern. The PC test and automatic test are separated using a high speed switching device which is capable of implementing a conversion without a signal distortion between the signal lines extended from the chip sets and the pattern generation substrate. Therefore, in the present invention, it is possible to enhance a test performance and decrease the test time and error ratio and cost of the products.

Claims4

Dependent claims

A PC and ATE integrated chip test equipment for testing a chip device, comprising:

a PC(Personal Computer) test equipment which tests a chip device under a PC environment formed of a CPU and chip sets;
a pattern generation substrate in which a processor is designed in an EPLD in order for a chip device to be pattern-programmed;
an ATE(Automatic Test Equipment) which generates a test pattern using the pattern generation substrate and performs a test using the generated test pattern;
and
a power generation unit which supplies a power to the PC test equipment and ATE for thereby performing two processes of the PC test and ATE operation in one equipment.

2 more elements

Dependencies are inferred from the claim text.

PC and ATE integrated chip test equipment

Life of this patent

PC and ATE integrated chip test equipment

Life of this patent

Abstract

Claims4