Information processor having delayed branch function

An information processor having a delayed branch function, the processor comprising:

• an instruction cache;
• and an instruction read circuit for reading instruction codes from the instruction cache by addressing the instruction cache, wherein the instruction read circuit comprises:
• a branch prediction circuit, including a storage in which a branch target address, branch history information, and delay slot information on a last position of delay slot instructions are stored in correspondence with an address of a branch instruction, outputting hit information as to whether or not an input address is coincident with the branch instruction address, when the coincidence is true, further outputting the delay slot information and prediction information on a presence of a branch based on the branch history information, and when the prediction information indicates that there is a branch, further outputting the branch target address;
• an incrementer for outputting a sequential address;
• and
• an address selection circuit for selectively outputting the branch target address or an output of the incrementer, based on the hit information, the delay slot information, and the prediction information.