Methods and apparatus for conversion of one or more data streams

3 The method of claim 2, further comprising:

• on a seventh clock count, shifting said first bit from said first data stream into a seventh storage position, shifting said second bit from said first data stream to said sixth storage position, shifting said third bit from said first data stream into said fifth storage position, and loading a fourth bit from said first data stream into said fourth storage position;
• and
• on an eighth clock count, shifting said first bit from said first data stream into an eighth storage position, shifting said second bit from said first data stream into said seventh storage position, shifting said third bit from said first data stream into said sixth storage position;
• and shifting said fourth bit from said first data stream into said fifth storage position.

4 The method of claim 3, further comprising:

• on a ninth clock count, shifting said second bit from said first data stream into said eighth storage position, shifting said third bit from said first data stream into said seventh storage position, shifting said fourth bit from said first data stream into said sixth storage position, loading a fifth bit from said first data stream into said fifth storage position, and loading a first bit from a second data stream into said first storage position;
• on a tenth clock count, shifting said third bit from said first data stream into said eighth storage position, shifting said fourth bit from said first data stream into said seventh storage position, shifting said fifth bit from said first data stream into said sixth storage position, and shifting said first bit from said second data stream into said second storage position;
• on an eleventh clock count, shifting said fourth bit from said first data stream into said eighth storage position, shifting said fifth bit from said first data stream into said seventh storage position, loading a sixth bit from said first data stream into said sixth storage position, shifting said first bit from said second data stream into said third storage position, and loading a second bit from said second data stream into said second storage position;
• and
• on a twelfth clock count, shifting said fifth bit from said first data stream into said eighth storage position, shifting said sixth bit from said first data stream into said seventh storage position, shifting said first bit from said second data stream into said fourth storage position, and shifting said second bit from said second data stream into said third storage position.

5 The method of claim 4, further comprising:

• on a thirteenth clock count, shifting said sixth bit from said first data stream into said eighth storage position, loading a seventh bit from said first data stream into said seventh storage position, shifting said first bit from said second data stream into said fifth storage position, shifting said second bit from said second data stream into said fourth storage position, and loading a third bit from said second data stream into said third storage position;
• on a fourteenth clock count, shifting said seventh bit from said first data stream into said eighth storage position, shifting said first bit from said second data stream into said sixth storage position, shifting said second bit from said second data stream into said fifth storage position, and shifting said third bit from said second data stream into said fourth storage position;
• on a fifteenth clock count, loading a eighth bit from said first data stream into said eighth storage position, shifting said first bit from said second data stream into said seventh storage position, shifting said second bit from said second data stream into said sixth storage position, shifting said third bit from said second data stream into said fifth storage position, and loading a fourth bit from said second data stream into said fourth storage position;
• on a sixteenth clock count, shifting said first bit from said second data stream into said eighth storage position, shifting said second bit from said second data stream into said seventh storage position, shifting said third bit from said second data stream into said sixth storage position, and shifting said fourth bit from said second data stream into said fifth storage position;
• on a seventeenth clock count, loading a ninth bit from said first data stream into said first storage position, shifting said second bit from said second data stream into said eighth storage position, shifting said third bit from said second data stream into said seventh storage position, shifting said fourth bit from said second data stream into said sixth storage position, and loading a fifth bit from said second data stream into said fifth storage position;
• on a eighteenth clock count, shifting said ninth bit from said first data stream into said second storage position, shifting said third bit from said second data stream into said eighth storage position, shifting said fourth bit from said second data stream into said seventh storage position, and shifting said fifth bit from said second data stream into said sixth storage position;
• on a nineteenth clock count, shifting said ninth bit from said first data stream into said third storage position, loading a tenth bit from said first data stream into said second storage position, shifting said fourth bit from said second data stream into said eighth storage position, shifting said fifth bit from said second data stream into said seventh storage position, and loading a sixth bit from said second data stream into said sixth storage position;
• on a twentieth clock count, shifting said ninth bit from said first data stream into said fourth storage position, shifting said tenth bit from said first data stream into said third storage position, shifting said fifth bit from said second data stream into said eighth storage position, and shifting said sixth bit from said second data stream into said seventh storage position;
• on a twenty-first clock count, shifting said ninth bit from said first data stream into said fifth storage position, shifting said tenth bit from said first data stream into said fourth storage position, loading a eleventh bit from said first data stream into said third storage position, shifting said sixth bit from said second data stream into said eighth storage position, and loading a seventh bit from said second data stream into said seventh storage position;
• on a twenty-second clock count, shifting said ninth bit from said first data stream into said sixth storage position, shifting said tenth bit from said first data stream into said fifth storage position, shifting said eleventh bit from said first data stream into said fourth storage position, and shifting said seventh bit from said second data stream into said eighth storage position;
• and
• on a twenty-third clock count, shifting said ninth bit from said first data stream into said seventh storage position, shifting said tenth bit from said first data stream into said sixth storage position, shifting said eleventh bit from said first data stream into said fifth storage position, loading an twelfth bit from said first data stream into said fourth storage position, and loading an eighth bit from said second data stream into said eighth storage position.

6 A method for use in taking sets of N bits from D input data streams to form a single data stream, comprising:

• loading a first bit from a first of the D input data streams into a first storage position on a first clock count;
• shifting said first bit from said first of the D input data streams through at least [((D−1)×N)−D/2+1]storage positions during a set of [((D−1)×N)−D/2+1] clock counts starting after said first clock count;
• and
• conducting D simultaneous load operations wherein during each of said load operations a bit from each of said D input data streams is loaded into a different storage position.

9 The method of claim 7, further comprising:

• loading a first bit from a second of said input data streams into said first storage position on a N+1 clock count;
• shifting said first bit from said second of the D input data streams through said additional [(D−1)×(N−1)] storage positions during a set of [(D−1)×(N−1)] clock counts starting after said N+1 clock count;
• loading a second bit from said second of said input data streams into said storage position D at clock count N+D+1;
• and
• loading a third bit from said second of said input data streams into said storage position 2D−1 at clock count N+2D+1.

A method for use in converting a data stream into multiple data streams, comprising:

• on a first clock count, loading a first bit from a data stream into a first storage position;
• on a second clock count, shifting said first bit into a second storage position and loading a second bit from said data stream into said first storage position;
• and
• on a third clock count, loading a third bit from said data stream into a third storage position.

An apparatus capable of performing a method for use in taking sets of N bits from D input data streams to form a single data stream, comprising:

• means for using a first bit from a first of the D input data streams to fill a first storage position on a first clock count;
• means for moving said first bit from said first of the D input data streams through at least [((D−1)×N)−D/2+1] storage positions during a set of [((D−1)×N)−D/2+1] clock counts starting after said first clock count;
• and
• means for implementing D simultaneous load operations wherein during each of said load operations a bit from each of said D input data streams is loaded into a different storage position.

A computer program product in a computer readable medium for use in ttking sets of N bits from D input data streams to form a single data stream, comprising:

• first instructions for taking a first bit from a first of D input data streams to fill a first storage position on a first clock count;
• second instructions for moving said first bit from said first of said D input data streams through at least [((D−1)×N)−D/2+1] storage positions during a set of [((D−1)×N)−D/2+1] clock counts starting after said first clock count;
• and
• third instructions for implementing D simultaneous load operations wherein during each of said load operations a bit from each of said D input data streams is loaded into a different storage position.

An apparatus for use in converting sets of N bits from D input data streams iito a single output data stream, comprising:

• a clock;
• a load register connected to said clock;
• and
• a shift register connected to said lock and to said load register, wherein said shift register includes a plurality of shift register elements;
• wherein said clock, said load register and said shift register are operative to:
• load a first bit from a first of said D input data streams into a first of the plurality of shift register elements on a first clock count;
• shift said first bit from said first of the D input data streams through at least [(D−1)×(N−1)] of the plurality of shift register elements during a set of [(D−1)×(N−1)] clock counts starting after said first clock count;
• and
• conduct D simultaneous load operations wherein during each of said load operations a bit from each of said D input data streams is loaded into a different one of said plurality of shift register elements.

An apparatus for use in converting D sets of N bits from an input data stream into D output data streams, comprising:

• a clock;
• a load register connected to said clock;
• and
• a D number of shift registers connected to said clock and to said load register, wherein each of said D number of shift registers includes a plurality of shift register elements;
• wherein said clock, said load register and said D number of shift registers are operative to:
• starting at a first clock count, load a bit from a first set of N different bit positions of said input data stream into a first set of N/2 shift register elements during a first set of N clock counts, wherein two bits from said input data stream are loaded into each of said first set of N/2 shift register elements;
• and
• starting at an N+1 clock count, load a bit from a second set of N different bit positions of said input data stream into a second set of N/2 shift register elements during a second set of N clock counts, wherein two bits from said input data stream are loaded into each of said second set of N/2 shift register elements.