Method and apparatus for characterizing timing-sensitive digital logic circuits

A method for characterizing a timing-sensitive digital logic circuit, the circuit receiving an input signal and producing an output signal in accordance with a clock signal, said method comprising:

• defining the clock signal with a set of clock signal parameters, the clock signal parameters including a timing of an active edge and a clock cycle;
• defining the input signal with a set of input signal parameters, the input signal parameters including a timing of transition edges;
• characterizing a first timing value of the circuit, the first timing value being a time period from the active edge of the clock signal to a first type of transition edge (first transition edge) of the input signal required to produce a valid output signal, said characterizing including:
• setting a set of input signal parameters such that the first transition edge is placed a selected time interval from the active edge of the clock signal;
• conducting simulation of the circuit;
• observing the output signal and determining validity of the output signal;
• shifting, by changing the input signal parameters, the first transition edge by a window having a given time width;
• simulating the circuit so as to observe and determine the validity of the output signal;
• iterating said shifting and said simulating until the validity of the output signal changes;
• and
• defining a solution window between the first transition edge yielding the last valid output signal and the first transition edge yielding the last invalid output signal.
• determining the first timing value with a predetermined resolution within the solution window;
• and
• characterizing a second timing value using the first timing value and the defined solution window, the second timing value being a time period from the active edge of the clock signal to a second type of transition edge (second transition edge) of the input signal required to produce a valid output signal.

An apparatus for characterizing a timing-sensitive digital logic circuit, the circuit receiving an input signal and producing an output signal in accordance with a clock signal, said apparatus comprising:

• means for defining a clock signal with a set of clock signal parameters, the clock signal parameters including a timing of an active edge and a clock cycle;
• means for defining an input signal with a set of input signal parameters, the input signal parameters including a timing of transition edges;
• and
• means for characterizing a timing value of the circuit, the timing value being a time period from the active edge of the clock signal to a transition edge of the input signal required to produce a valid output signal, said means for characterizing including:
• means for setting a set of input signal parameters such that the transition edge is placed a selected time interval from the active edge of the clock signal;
• means for conducting simulation of the circuit;
• means for observing the output signal and determining validity of the output signal;
• means for shifting the transition edge by a window having a given time width;
• means for simulating the circuit so as to observe and determine the validity of the output signal;
• means for iteratively executing said means for shifting and said means for simulating by doubling the time width of the window for each iteration unless the doubled time width exceeds half the clock cycle and until the validity of the output signal changes;
• and
• means for defining a solution window between the transition edge yielding the last valid output signal and the transition edge yielding the last invalid output signal.

An apparatus for characterizing a timing-sensitive digital logic circuit, the circuit receiving an input signal and producing an output signal in accordance with a clock signal, said apparatus comprising:

• means for defining the clock signal with a set of clock signal parameters, the clock signal parameters including a timing of an active edge and a clock cycle;
• means for defining the input signal with a set of input signal parameters, the input signal parameters including a timing of transition edges;
• means for characterizing a first timing value of the circuit, the first timing value being a time period from the active edge of the clock signal to a first type of transition edge (first transition edge) of the input signal required to produce a valid output signal, said means for characterizing including:
• means for setting a set of input signal parameters such that the first transition edge is placed a selected time interval from the active edge of the clock signal;
• means for conducting simulation of the circuit;
• means for observing the output signal and determining validity of the output signal;
• means for shifting, by changing the input signal parameters, the first transition edge by a window having a given time width;
• means for simulating the circuit so as to observe and determine the validity of the output signal;
• means for iteratively executing said means for shifting and said means for simulating until the validity of the output signal changes;
• and
• means for defining a solution window between the first transition edge yielding the last valid output signal and the first transition edge yielding the last invalid output signal.
• means for determining the first timing value with a predetermined resolution within the solution window;
• and
• means for characterizing a second timing value using the first timing value and the defined solution window, the second timing value being a time period from the active edge of the clock signal to a second type of transition edge (second transition edge) of the input signal required to produce a valid output signal.

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for characterizing a timing-sensitive digital logic circuit, the circuit receiving an input signal and producing an output signal in accordance with a clock signal, said method comprising:

• defining a clock signal with a set of clock signal parameters, the clock signal parameters including a timing of an active edge and a clock cycle;
• defining an input signal with a set of input signal parameters, the input signal parameters including a timing of transition edges;
• and
• characterizing a timing value of the circuit, the timing value being a time period from the active edge of the clock signal to a transition edge of the input signal required to produce a valid output signal, said characterizing including:
• setting a set of input signal parameters such that the transition edge is placed a selected time interval from the active edge of the clock signal;
• conducting simulation of the circuit;
• observing the output signal and determining validity of the output signal;
• shifting, by changing the input signal parameters, the transition edge by a window having a given time width;
• simulating the circuit so as to observe and determine the validity of the output signal;
• iterating said shifting and said simulating by doubling the time width of the window for each iteration unless the doubled time width exceeds half the clock cycle and until the validity of the output signal changes;
• and
• defining a solution window between the transition edge yielding the last valid output signal and the transition edge yielding the last invalid output signal.

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for characterizing a timing-sensitive digital logic circuit, the circuit receiving an input signal and producing an output signal in accordance with a clock signal, said method comprising:

• defining the clock signal with a set of clock signal parameters, the clock signal parameters including a timing of an active edge and a clock cycle;
• defining the input signal with a set of input signal parameters, the input signal parameters including a timing of transition edges;
• characterizing a first timing value of the circuit, the first timing value being a time period from the active edge of the clock signal to a first type of transition edge (first transition edge) of the input signal required to produce a valid output signal, said characterizing including:
• setting a set of input signal parameters such that the first transition edge is placed a selected time interval from the active edge of the clock signal;
• conducting simulation of the circuit;
• observing the output signal and determining validity of the output signal;
• shifting, by changing the input signal parameters, the first transition edge by a window having a given time width;
• simulating the circuit so as to observe and determine the validity of the output signal;
• iterating said shifting and said simulating until the validity of the output signal changes;
• and
• defining a solution window between the first transition edge yielding the last valid output signal and the first transition edge yielding the last invalid output signal.
• determining the first timing value with a predetermined resolution within the solution window;
• and
• characterizing a second timing value using the first timing value and the defined solution window, the second timing value being a time period from the active edge of the clock signal to a second type of transition edge (second transition edge) of the input signal required to produce a valid output signal.