Loading patent…
AssigneeNEC Electronics Corporation
InventorsToshihiro Ueda, Hiroshi Kikuchi
Estimating the term…
A plurality of data code files including addresses and data to be written to the addresses are prepared. Next, a simulation model of a memory macro (memory macro model) is set to write mode. Then, an address value and data value are extracted from a verification pattern at a write-in operation in the first clock cycle after the write mode has been set. A necessary data code file is selected from the plurality of data code files based on the extracted search key. Finally, data are written at once to the simulation model of the memory macro according to contents of the selected data code file.
A logic simulation method for a simulation model including a memory macro, comprising steps of:
A computer program product, in a computer-readable medium, for performing a simulation on a simulation model including a memory macro and a plurality of data code files each having a plurality of data, the computer program product comprising:
A method for performing logic simulation on a simulation model that has a memory macro and a data processing circuit coupled to receive and manipulates data read out from said memory macro, comprising:
Dependencies are inferred from the claim text.