Lithography device for semiconductor circuit pattern generator

A method of making an integrated circuit comprising the steps of:

• forming a substrate having a thickness of less than about 50 μm;
• forming semiconductor devices on a principal surface of the substrate;
• depositing a low stress insulating membrane over the semiconductor devices;
• and
• forming electrical interconnections in the membrane extending between the semiconductor devices.

A method for forming a flat panel display comprising the steps of:

• providing a substrate;
• forming a layer of a release agent on a surface of the substrate;
• forming a membrane less than about 100 μm thick and including integrated circuitry on the layer of release agent;
• selectively depositing color phosphors on localized portions of the membrane, thereby forming pixels;
• and
• releasing the membrane from the substrate by activating the release agent.

A method of making a stacked integrated circuit structure comprising the steps of:

• forming first and second flexible membranes each including a plurality of electrically interconnected semiconductor devices;
• bonding a principal surface of the first flexible membrane to the second flexible membrane;
• and
• interconnecting at least one semiconductor device in the first flexible membrane to a semiconductor device in the second flexible membrane.

A method of testing an integrated circuit having electrical contracts formed thereon spaced apart a distance of less than about 50 μm, comprising the steps of:

• providing a flexible tester membrane including a plurality of probe points formed on one surface thereof, and a plurality of integrated circuits attached to an opposing surface thereof for providing test signals to the probe points;
• electrically interconnecting the integrated circuits to the probe points by conductors extending through the tester membrane:
• and
• providing at least two of the probe points spaced apart less than about 50 μm.

An integrated circuit assembly comprising:

• a plurality of vertically stacked flexible membranes each having semiconductor devices and interconnections between the semiconductor devices formed on the membrane;
• an array of optical transmitter semiconductor devices formed on one of the membranes;
• and
• an array of optical receiver semiconductor devices formed on a second of the membranes and aligned with the array of optical transmitter devices to receive optical transmissions of data therefrom.

A method of making an integrated circuit interconnect membrane comprising:

• providing a substrate having a planner principal surface;
• coating the principal surface with a release agent;
• forming a flexible dielectric membrane on the release agent;
• forming conducting traces on the membrane;
• attaching integrated circuits to the conducting traces;
• and
• releasing the membrane from the substrate by activating the release agent.

A lift-off method of forming a conductive metal trace in a flexible membrane for electrical interconnection of integrated circuits mounted on the membrane, comprising the steps of:

• forming a resist layer on a surface of the membrane;
• patterning the resist layer, exposing a portion of the surface;
• isotopically etching the portion of the membrane at the exposed surface portion thereof, undercutting the resist layer and forming a groove in the membrane;
• depositing a layer of metal over the resist layer and in the groove;
• removing the resist layer and overlying metal layer;
• and
• forming a dielectric layer overlying the groove.

A method of forming a field effect transistor having a narrow gate and opposed gate contact, comprising the steps of:

• forming a silicon layer less than about 10 μm thick;
• forming a gate electrode over the principal surface of the silicon layer;
• forming a low stress dielectric layer less than about 10 μm thick over the silicon layer and over the gate electrode;
• forming doped regions in the silicon layer;
• etching a groove in the silicon layer from the surface opposing the principal surface thereof in a portion of the silicon layer underlying the gate electrode;
• depositing metal in the groove to a predetermined depth;
• etching away the opposing surface of the silicon layer to the predetermined depth;
• depositing a mask layer on the etched-away surface;
• patterning the mask layer, thereby exposing portions of the etched-away surface;
• forming additional doped regions in the silicon layer at the exposed portions of the etched-away surface;
• removing the mask layer;
• and
• etching away additional portions the etched-away surface to the bottom of the groove, thereby removing all of the deposited metal.

A method of forming a multi-chip module using a flexible membrane to interconnect the chips, comprising the steps of:

• providing a flexible membrane;
• forming conductive traces on the membrane;
• and
• mounting a plurality of integrated circuit die to the membrane at the traces.

A method of aligning a lithographic fabrication tool to a substrate to be exposed by the tool, comprising the steps of:

• providing a first conductive coil pattern on a surface of the substrate;
• applying electrical current to the coil pattern;
• providing a second conductive coil on a surface of the tool;
• bringing the surface of the tool near to the surface of the substrate;
• and
• sensing an electromagnetic field generated by the first coil in the second coil.

A method of forming a transistor, comprising the steps of:

• providing a flexible membrane having a thin film of semiconductor material formed on the membrane;
• forming a trench in the semiconductor material;
• doping portions of the semiconductor material;
• laterally growing extensions of the sidewalls of the trench, thereby narrowing the trench to a predetermined width;
• filling the remaining width of the trench with semiconductor material doped at a concentration differing from a doping level of the extensions;
• and
• forming an electrical contact to the filled portion of the trench through the flexible membrane.

A field effect transistor comprising:

• a flexible dielectric membrane having a principal surface;
• a semiconductor film formed on the principal surface of the membrane, the semiconductor film including at least three doped layers;
• a contact to a first of the three doped layers formed through the membrane;
• a contact to a second of the doped layers formed on a principal surface of the semiconductor film;
• an insulating layer formed over an edge of the semiconductor film;
• and
• a gate electrode formed overlying the insulating layer.

A bipolar transistor comprising:

• a flexible dielectric membrane having a principal surface;
• a semiconductor film formed on the principal surface and including at least three doped layers;
• a contact to the first of the three layers formed through the membrane;
• and
• contacts to the second and the third layers.

A method of forming an interconnect structure for a circuit membrane, comprising the steps of:

• providing a semiconductor film;
• forming a flexible dielectric membrane on a principal surface of the semiconductor film;
• forming a layer of amorphous silicon on the membrane;
• patterning the amorphous silicon layer to form trenches and vias therein;
• depositing a layer of metal over the patterned amorphous silicon;
• patterning the deposited layer of metal, thereby forming metal traces;
• forming a second layer of amorphous silicon overlying the traces;
• patterning the second layer of amorphous silicon;
• forming a second dielectric layer over the second patterned layer of amorphous silicon;
• forming etch vias penetrating the dielectric layer to the underlying second layer of amorphous silicon;
• and
• removing the first and second layers of amorphous silicon through the etch vias, thereby leaving the metal traces supported at the vias by the dielectric membrane and overlain by the dielectric layer.

A method of fabricating an integrated circuit comprising the steps of:

• providing a free standing membrane formed of a layer of low stress dielectric and a substrate layer;
• forming a plurality of transistors in the substrate layer;
• and
• forming interconnections on the dielectric layer between the transistors

A method of forming a field effect transistor comprising the steps of:

• providing a membrane comprising a semiconductor layer overlying a low stress dielectric layer;
• forming a drain region and a source region laterally spaced apart from the drain region in the semiconductor layer, a portion of the semiconductor layer between the source and drain regions being a gate region;
• forming an insulating layer overlying the semiconductor layer;
• and
• forming a gate electrode on the insulating layer, one edge of the gate electrode being in a plane defined by an interface of one of the source region or the drain region and the gate region, and a second edge of the gate electrode extending over the other of the drain region or source region.

A method of forming a transistor comprising the steps of:

• providing a flexible membrane including a low stress dielectric layer and a semiconductor layer;
• forming a first and a second doped regions in the semiconductor layer, the first and second doped regions being vertically spaced apart and separated by a control region;
• epitaxially growing an extension of the control region extending over an edge of the semiconductor layer and contacting edges of the first and second doped regions;
• and
• forming electrical contacts to the first and second doped regions and to extension of the control region.

A method of testing an integrated circuit comprising:

• providing a flexible free standing circuit membrane including a semiconductor layer and a flexible low stress dielectric layer, and having at least 100 probe points formed on its principal surface;
• providing a source of pressure against a back surface of the membrane, thereby contacting the integrated circuit being tested with the probe points;
• and
• moving the integrated circuit being tested laterally relative to the circuit membrane while in contact with the probe points.

A semiconductor processing lithography apparatus for maskless pattern generation comprising:

• an array of radiation source cells arranged in rows and columns, the array being formed on a flexible insulating membrane held in a support frame;
• control logic mounted on the membrane for controlling the cells, wherein each cell comprises:
• a source of radiation;
• a target on which the radiation is incident for generating X-rays;
• and
• an aperture for emitting the X-rays from the target onto a surface to be exposed.

A lithography pattern generating device comprising:

• an array of cells arranged in rows and columns, the array being formed on a flexible insulating membrane held in a support frame, each cell being individually controlled to permit passage of charged particles from an external source;
• and
• control logic mounted on the membrane for controlling each cell;
• wherein each cell comprises an aperture for emitting the particles onto a surface to be exposed.

A lithography pattern generating device comprising:

• an array of cells arranged in rows and columns, the array being formed on a flexible insulating membrane held in a support frame, each cell defining an aperture to permit passage of charged particles from a source;
• a movable shutter for covering each aperture;
• to block said passage;
• and
• control logic mounted on the membrane for controlling movement of each shutter.

A contact stepper printer lithography method comprising:

• providing a mask structure formed of a flexible membrane;
• bringing the mask structure adjacent to a substrate to be patterned;
• providing pressure against a backside of the mask structure thereby bringing a frontside of the mask structure to within a predetermined distance of the substrate;
• exposing a first portion of the substrate to a source of radiation propagating through the mask structure;
• moving the mask structure adjacent to a second portion of the substrate;
• and
• exposing the second portion to the source of radiation propagating through the mask structure.

A method of forming a lithographic fixed mask comprising the steps of:

• providing a membrane including a semiconductor layer on a first low stress dielectric layer;
• forming a metal layer on the semiconductor layer;
• patterning the metal layer, thereby removing portions thereof;
• selectively etching portions of the semiconductor layer underlying the removed portions of the metal layer;
• depositing a second low stress dielectric layer over the patterned semiconductor layer;
• and
• removing the first low stress dielectric layer.

A method of forming a fixed stencil lithographic mask comprising the steps of:

• providing a membrane including a semiconductor layer on a low stress dielectric layer;
• patterning the dielectric layer by etching away portions thereof;
• and
• selectively wet etching the silicon layer to remove portions thereof.

A method of forming a sensor diaphragm comprising the steps of:

• providing a semiconductor material substrate;
• forming a low stress dielectric layer on the substrate;
• and
• etching away a portion of the substrate, leaving a portion of the dielectric layer as a free standing diaphragm supported at its edges by the substrate.