Method and system to synchronize a multi-level memory

An apparatus comprising:

• a data packet processing device;
• a memory coupled to the device to store data packets external to the device;
• a counter coupled with the device and the external memory to count the number of data packets transferred to the external memory and to count the number of data packets transmitted from the external memory to an output port of the apparatus;
• and
• a controller coupled with the counter to check the counter each time a data packet is ready to be transmitted from the external memory to the output port to determine if the number of packets transferred to the external memory exceeds the number of packets transmitted from the external memory to the output port.

An article of manufacture comprising:

• a machine accessible medium including content that when accessed by a machine causes the machine to:
• store a data packet in a memory of a device;
• determine if the data packet has been transferred to the external memory;
• and if so,
• retrieve the data packet from the external memory and transfer the data packet from the external memory to an output port.

A system comprising:

• a first and second memory to store data packets;
• a processor coupled to the first memory and the second memory via a bus, and
• logic coupled to the first memory and the second memory, the logic including
• a counter to count the number of data packets transferred from the first memory to the second memory and to count the number of data packets transmitted from the second memory to an output port;
• and
• a controller to check the counter each time a data packet is ready to be transmitted from the second memory to the output port to determine if the number of data packets transferred from the first memory to the second memory exceeds the number of data packets transmitted from the second memory to the output port.