Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate, and a memory array made thereby

An array of electrically programmable and erasable memory devices comprising:

• a substrate of semiconductor material having a first conductivity type and a surface;
• spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
• and
• each of the active regions including a plurality of pairs of memory cells, wherein each of the memory cell pairs comprises:
• a trench formed into the surface of the substrate and including a pair of opposing sidewalls,
• a first region formed in the substrate underneath the trench,
• a pair of second regions formed in the substrate, with a pair of channel regions each formed in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, and wherein each of the channel regions includes a first portion that extends substantially along one of the opposing trench sidewalls and a second portion that extends substantially along the substrate surface,
• a pair of electrically conductive floating gates each having at least a lower portion thereof disposed in the trench adjacent to and insulated from one of the channel region first portions for controlling a conductivity of the one channel region first portion, and
• a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions for controlling a conductivity of the one channel region second portion, wherein there is at most only a partial vertical overlap between the control gates and the floating gates.

A method of forming a semiconductor memory cell, comprising:

• forming a trench into a surface of a semiconductor substrate, wherein the substrate has a first conductivity type;
• forming first and second spaced-apart regions of a second conductivity type in the substrate with the first region formed underneath the trench, wherein a channel region is defined in the substrate between the first and second regions such that the channel region includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate;
• forming an electrically conductive floating gate having at least a lower portion thereof disposed in the trench adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion;
• and
• forming an electrically conductive control gate disposed over and insulated from the channel region second portion for controlling a conductivity of the channel region second portion, wherein there is at most only a partial vertical overlap between the control gate and the floating gate.

A method of forming an array of electrically programmable and erasable memory devices, comprising:

• forming spaced apart isolation regions on a semiconductor substrate that are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, wherein the substrate has a surface and a first conductivity type;
• and
• forming a plurality of pairs of memory cells in each of the active regions, wherein the formation of each of the memory cell pairs includes:
• forming a trench into the surface of the substrate having a pair of opposing sidewalls,
• forming a first region in the substrate and underneath the trench,
• forming a pair of second regions in the substrate, with a pair of channel regions each defined in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, and wherein each of the channel regions includes a first portion that extends substantially along one of the opposing trench sidewalls and a second portion that extends substantially along the surface of the substrate,
• forming a pair of electrically conductive floating gates each having at least a lower portion thereof disposed in the trench adjacent to and insulated from one of the channel region first portions for controlling a conductivity of the one channel region first portion, and
• forming a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions for controlling a conductivity of the one channel region second portion, wherein there is at most only a partial vertical overlap between the control gates and the floating gates.