US 2003/0223285 A1 · Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations

Abstract

A nonvolatile memory device is described comprising a memory array, a row decoder and a column selector for addressing the memory cells of the memory array, and a biasing stage for biasing the array access device terminal of the addressed memory cell. The biasing stage is arranged between the column selector and the memory array and comprises a biasing transistor having a drain terminal connected to the column selector, a source terminal connected to the array access device terminal of the addressed memory cell, and a gate terminal receiving a logic driving signal, the logic levels of which are defined by precise and stable voltages and are generated by a logic block and an output buffer cascaded together. The output buffer may be supplied with either a read voltage or a program voltage supplied by a multiplexer. The biasing transistor may be either included as part of the column selector and formed by the selection transistor which is closest to the addressed memory cell or distinct from the selection transistors of the column selector.

Claims12

Dependent claims

A nonvolatile memory device comprising:

a memory array including a number of memory cells;
row decoding means;
column selection means connected to said memory array for addressing said memory cells;
biasing means arranged between said column selection meansand said memory array for biasing a current conduction terminal of an addressed memory cell, said biasing means having a cascode structure and including a biasing transistor means having a first current conduction terminal connected to said column selection means, a second current conduction terminal connected to said current conduction terminal of said addressed memory cell, and a control terminal receiving a driving signal, said biasing means further including driving means receiving at least one control signal indicating the operation to be performed on said addressed memory cell, a first reference voltage and at least a second reference voltage, and generating said driving signal for said biasing transistor means, said driving signal assuming levels which are defined by said first or by said second reference voltage according to said control signal.

1 more element

Dependencies are inferred from the claim text.

Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations

Life of this patent

Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations

Life of this patent

Abstract

Claims12