ESD protection circuit with whole-chip ESD protection
AssigneeIndustrial Technology Research Institute
InventorsZi-Ping Chen, Chyh-Yih Chang, Ming-Dou Ker
Life of this patent
Estimating the term…
Abstract
An ESD protection circuit with whole-chip ESD protection. A plurality of ESD protection devices, apart from an ESD detection circuit, can be MOS transistors connected between the input/output pads and the VDD/VSS lines or a power rail clamp circuit between the VDD and VSS lines. The ESD detection circuit is connected between the VDD and VSS lines. When an ESD event occurs and an ESD current is bypassed to the power line, the ESD detection circuit generates a plurality of enabling signals to simultaneously enable the ESD protection devices, which provides a plurality of discharge paths to bypass the ESD current.
Claims17
An electrostatic discharge (ESD) protection circuit used in an integrated circuit with a pad, a VDD line and a VSS line, comprising:
- a plurality of ESD protection devices connected between two of the pads, the VDD line and the VSS line, respectively;
- and
- an ESD detection circuit connected between the VDD line and the VSS line, for generating enabling signals as an ESD current with respect to an ESD-stress mode happens in the pad and flows to the VDD line or VSS line, the enabling signals enabling the ESD protection devices and activating at least two discharge paths constituted by the ESD protection devices to bypass the ESD current.
An electrostatic discharge (ESD) protection circuit used in an integrated circuit with a plurality of pads, a VDD line and a VSS line, comprising:
- a power rail clamp circuit connected between the VDD line and the VSS line;
- a plurality of first ESD protection devices implemented by PMOS transistors and connected between the corresponding pads and the VDD line;
- and
- a plurality of second ESD protection devices implemented by NMOS transistors and connected between the corresponding pads and the VSS line;
- and
- an ESD detection circuit connected between the VDD line and the VSS line, for generating enabling signals as an ESD current with respect to an ESD-stress mode flows from the pad and to the VDD or VSS line through one of the first ESD protection devices and the second ESD protection devices, the enabling signals enabling at least two the first ESD protection devices, the second ESD protection devices and the power rail clamp circuit to bypass the ESD current.
Dependencies are inferred from the claim text.