Processor system with coprocessor
AssigneeHitachi, Ltd.
InventorsKazuhiko Tanaka, Koji Hosogi, Sigeki Higashijima, Kiyokazu Nishioka
Life of this patent
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Abstract
A processor has a data cache that is connected to a coprocessor via a bus, in which the coprocessor writes results of operations performed within the coprocessor in the data cache inside the processor. The data cache is equipped with a function to write data in a tag memory or a data memory according to a write request from the bus, and the coprocessor is equipped with an address generation device that is capable of designating an address of the data cache as a write address.
Claims23
A system comprising:
- a first processor having a first memory;
- a second processor for performing a specified processing;
- and
- a bus that connects the first processor and the second processor,
- wherein the second processor includes a module that generates an address for accessing a device that is connected to the bus, and
- the second processor transfers an operation result obtained by the second processor to the first memory based on the address generated by the module.
A coprocessor for a processor having a first memory, the coprocessor comprising an address generation module that is required to write a result of an operation via a bus connected to the processor.
A processing method for a system comprising a first processor having a first memory, a second processor for performing a specified processing, and a bus that connects the first processor and the second processor, the processing method comprising the steps of:
- making a module included in the second processor generate an address for accessing a device that is connected to the bus;
- and
- making the second processor transfer an operation result obtained by the second processor to the first memory based on the address generated.
Dependencies are inferred from the claim text.