Power consumption management in a video graphics accelerator
AssigneeATI Technologies, Inc.
InventorsVladimir Giemborek, Syed Hussain, David Chih
Life of this patent
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Abstract
A method and apparatus matches one or more clock speeds used in, or used by, a graphics accelerator so as to match graphics processing requirements to the speed of the clock source or sources. Clock speed is adjusted under software control to match current requirements. Power is conserved by reducing clock speeds from unnecessarily high rates to a rate that can satisfy current display mode settings and other graphics processing demands.
Claims15
A method for reducing power consumption for a portable device employing a graphics processing circuit comprising:
- determining, by a processor, graphics processing requirements of said graphics processing circuit from, at least one display mode setting for a display device;
- and
- varying, under control of the processor, the frequency of at least one clock source used by said graphics processing circuit so as to substantially match the speed of said at least one clock source to graphics processing requirements.
A graphics processing circuit comprised of:
- at least one, programmable clock source means for changing the frequency of a graphics processor clock source, to match graphics processing requirements, in response to signals from a CPU.
A graphics processing circuit comprised of:
- at least one, programmable phased-locked loop clock source having an associated control register into which data is written by a processor to vary the speed of said programmable phased-locked loop to match the clock speed of said programmable phased-locked loop to graphics processing requirements of said graphics processing circuit.
A graphics processing circuit comprised of:
- clock source multiplexor means for providing an interim clock source to at least one of:
- a graphics processing engine and a frame buffer memory, during at least part of the time that a programmable clock source for said graphics processing engine or a frame buffer memory is changed in response to signals from a CPU to said programmable clock source.
A graphics processing circuit comprised of:
- a multiplexor, having a plurality of inputs, each of which is operatively coupled to at least one clock source, at least one output, coupled to at least one of a graphics processing engine and a frame buffer memory, said multiplexor in response to signals from a CPU to which said clock source multiplexor is operative coupled.
A computer device comprised of:
- a system bus;
- system memory coupled to said system bus;
- a host CPU coupled to said system bus;
- an input/output device coupled to said system bus;
- a display device, said display device having graphics processing requirements provided by a graphics accelerator;
- a power-consumption adjustable, graphics accelerator coupled to said system bus and in communication with said host CPU, said power-consumption adjustable graphics accelerator having at least one of:
- a programmable graphics processing clock source and a programmable frame buffer memory clock source;
- said at least one programmable clock source being responsive to signals from said host CPU so as to adjust the speed of said at least one programmable graphics processing clock source and a programmable frame buffer memory clock source to match graphics processing requirements of said computer device.
Dependencies are inferred from the claim text.