Phase locked loop (PLL) frequency synthesizer and method

A phase locked loop (PLL) frequency synthesizer comprising:

• a primary phase locked loop circuit having a voltage controlled oscillator (VCO) circuit and a programmable divider circuit for establishing a voltage controlled oscillator output and a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency;
• and
• a secondary phase locked loop circuit operatively connected to the primary phase locked loop circuit, and operative for receiving and isolating an external reference signal that has been recovered from received data of a telecommunications system and may have been corrupted from noise and spurious signals and used for the primary phase locked loop circuit, and including a frequency controlled, temperature compensated crystal oscillator for generating a voltage controlled, clean reference signal wherein said secondary phase locked loop circuit filters and synchronizes the clean reference signal with the external reference signal for producing the reference signal output to the phase locked loop circuit.

A method of generating a high frequency signal comprising the steps of:

• generating an output signal from a voltage controlled oscillator of a primary phase locked loop (PLL) circuit having a programmably divided, voltage controlled oscillator output and a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency;
• and
• isolating an external reference signal used for the phase locked loop circuit by generating a voltage controlled, clean reference signal and filtering and synchronizing the clean reference signal with the external reference signal within a secondary phase locked loop circuit to produce the reference signal output to the primary phase locked loop circuit.

A method of generating a high frequency signal comprising the steps of:

• generating an output signal from a voltage controlled oscillator of a primary phase locked loop (PLL) circuit having a programmably divided, voltage controlled oscillator output and a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency;
• and
• isolating an external reference signal that had been recovered from received data of a communications system that may have been corrupted with noise and spurious signals and used for the phase locked loop circuit by generating a clean reference signal from a voltage controlled, temperature compensated crystal oscillator and filtering and synchronizing the clean reference signal with the external reference signal within a secondary phase locked loop circuit to produce the reference signal output to the primary phase locked loop circuit.