Semiconductor device and method of fabricating the same
AssigneeElpida Memory, Inc.
InventorRyoichi Nakamura
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Abstract
A semiconductor device includes a PMOS transistor region in which a PMOS transistor is fabricated, an N well diffusion layer region in which an N well diffusion layer is fabricated, a P well diffusion layer region in which a P well diffusion layer is fabricated, and at least one NMOS transistor region in which an NMOS transistor is fabricated, wherein each of the NMOS transistor region and the P well diffusion layer region includes a pocket boron region in which pocket boron is implanted, and a P well is formed across the P well diffusion layer region and the NMOS transistor region such that the P well is electrically connected to the P well diffusion layer region.
Claims10
A semiconductor device including a PMOS transistor region in which a PMOS transistor is fabricated, an N well diffusion layer region in which an N well diffusion layer is fabricated, a P well diffusion layer region in which a P well diffusion layer is fabricated, and an NMOS transistor region in which an NMOS transistor is fabricated,
- wherein each of said NMOS transistor region and said P well diffusion layer region includes a P-type impurity region in which a P-type impurity is implanted, and
- a P well is formed across said P well diffusion layer region and said NMOS transistor region such that said P well is electrically connected to said P well diffusion layer region.
A method of fabricating a semiconductor device including a PMOS transistor region in which a PMOS transistor is fabricated, an N well diffusion layer region in which an N well diffusion layer is fabricated, a P well diffusion layer region in which a P well diffusion layer is fabricated, and at least one NMOS transistor region in which an NMOS transistor is fabricated,
- said method including the steps of:
- (a) implanting N-type impurity into a substrate to concurrently form a lightly doped drain (LDD) region of said NMOS transistor and a pocket region of said PMOS transistor area;
- and
- (b) implanting a P-type impurity into said NMOS transistor region and said P well diffusion layer region to electrically connect a P well formed across said P well diffusion layer region and said NMOS transistor region, to said P well diffusion layer region.
Dependencies are inferred from the claim text.