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US 2003/0222279 A1Published application
Ferroelectric memory integrated circuit with improved reliability
AssigneeInfineon Technologies AG
InventorsMichael Jacob, Uwe Wellhausen
Life of this patent
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Abstract
An IC with memory cells arranged in a chained architecture is disclosed. The top local interconnect between the top capacitor electrodes and active area is achieved by using a strap. The use of a strap eliminates the need for additional metal layer which reduces manufacturing costs. Furthermore, sidewall spacers are used to isolate the strap from the different layers of the capacitors. The use of spacers advantageously enables the strap to be self-aligned.
Claims21
An integrated circuit (IC) comprising:
- a first memory cell including a first transistor with first and second diffusion regions and a first capacitor with a dielectric layer between top and bottom electrodes;
- a second memory cell including a second transistor with first and second diffusion regions and a second capacitor with a dielectric layer between top and bottom electrodes;
- the second diffusion regions of the first and second transistors form a common diffusion region;
- and
- a strap coupling the top electrodes of the first and second capacitors to a first contact which is coupled to the common diffusion region, the strap isolated from the capacitors by spacers located on sidewalls of the capacitors.
2 more elements
Dependencies are inferred from the claim text.