Loading patent…
AssigneeInternational Business Machines Corporation
InventorsKerry Christopher Imming, Christopher Jon Johnson, Tolga Ozguner
Estimating the term…
A method and apparatus are provided for implementing chip-to-chip interconnect bus initialization. The chip-to-chip interconnect bus includes first and second unidirectional buses for full duplex communications between two chips. A lower than normal bus frequency is used during the initialization process. A transmit initialization sequencer of a source transmits predefined SYNC symbols on the connected unidirectional bus. A receive initialization sequencer of a destination chip checks for a defined number of valid SYNC or IDLE symbols. When the receive initialization sequencer of a destination detects the defined number of valid SYNC or IDLE symbols, the receive initialization sequencer triggers a transmit initialization sequencer of the destination to transmit IDLE symbols on the connected unidirectional bus. The transmitted IDLE symbols are detected by a receive initialization sequencer at the source, indicating that both ends of the interconnect bus have synchronized. Once link synchronization is established, the source transmits configuration information to the destination using normal bus messages. Programmable delay elements and configuration registers are set.
Apparatus for implementing chip-to-chip interconnect bus initialization, said chip-to-chip interconnect bus comprising a first unidirectional bus and a second unidirectional bus for full duplex communications between two chips, said initialization apparatus comprising:
A method for implementing chip-to-chip interconnect bus initialization comprising the steps of:
Dependencies are inferred from the claim text.