Sacrificial feature for corrosion prevention during CMP

A semiconductor device fabricated at least in part by performing chemical-mechanical planarization (CMP) comprising:

• a desired semiconductor feature having an unbalanced geometric pattern including a metallic line ending in at least one tip, the at least one tip susceptible to corrosion resulting from performing the CMP;
• and,
• a sacrificial semiconductor feature located off the metallic line and attracting charge induced during the CMP that is otherwise attracted by the at least one tip of the desired semiconductor feature, such that presence of the sacrificial semiconductor feature substantially prevents corrosion of the at least one tip.

A method comprising:

• providing a semiconductor layout having a desired semiconductor feature and a sacrificial semiconductor feature;
• and,
• fabricating a semiconductor device using the semiconductor layout, including performing chemical-mechanical planarization (CMP), the sacrificial semiconductor feature acting to prevent corrosion of the desired semiconductor feature resulting from performing the CMP.