Dual metal gate transistors for CMOS process

A semiconductor device in a semiconductor substrate having a first well of a first conductivity type and a second well of a second conductivity type, comprising:

• a gate dielectric over at least a portion of the first well and the second well;
• a first gate over the first well and the gate dielectric, the first gate having a first region of a first metal type and a second region of a second metal type different from the first metal type, the first region being on the gate dielectric;
• a first source and a first drain formed in the first well adjacent to the first gate;
• a second gate over the second well and the gate dielectric, the second gate of the second metal type, the second metal type being different from the first metal type;
• a second source and a second drain formed in the second well adjacent to the second gate.

A method for forming a first transistor of a first conductivity type and a second transistor of a second conductivity type in a semiconductor substrate having a first well of the first conductivity type and a second well of the second conductivity type, comprising the steps of:

• forming a first removable gate over the first well and a second removable gate over the second well;
• forming a first source and a first drain of the second conductivity type in the first well adjacent to the first removable gate;
• forming a second source and second drain of the first conductivity type in the second well adjacent to the second removable gate;
• removing the first and second removable gates;
• forming a gate dielectric over the first and second wells;
• forming a first metal layer of a first metal type over the gate dielectric;
• removing a first portion of the first metal layer, the first portion of the first metal layer being over the second well;
• then forming a second metal layer of a second metal type different from said first metal type over the first and second wells;
• and
• removing a first portion of the of the second metal layer, the first portion of the second metal layer being between the first and second wells;
• whereby a first transistor is formed in the second well and a second transistor is formed in the first well.