US 2003/0216029 A1 · METHOD OF SELECTIVELY ALLOYING INTERCONNECT REGIONS BY DEPOSITION PROCESS

Abstract

A metal interconnect structure and method for making the same provides an alloying elements layer that lines a via in a dielectric layer. The alloying element layer is therefore inserted at a critical electromigration failure site, i.e., at the fast diffusion site below the via in the underlying metal. Once the copper fill is performed in the via, an annealing step allows the alloying element to go into solid solution with the copper in and around the via. The solid solution of the alloying element and copper at the bottom of the via in the copper line improves the electromigration reliability of the structure.

Claims19

Dependent claims

A metal interconnect structure comprising:

a copper line;
a dielectric layer over the copper line;
a via extending through the dielectric layer to the copper line;
a copper alloying element layer comprising an alloying element lining the via and covering the copper line exposed by the via;
a conductive plug filling the via;
and
a solid solution of copper and the alloying elements in the copper line only in an area of the copper line adjacent the conductive plug.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

09/884,027Filed 20 Jun 2001

Published

20 Nov 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10W 20/033
Of conductive barrier, adhesion or liner layers: in openings in dielectrics
H10W 20/0526
By treatments not introducing additional elements therein: by thermal treatment thereof
H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs
H10W 20/425
Characterised by their conductive parts: barrier, adhesion or liner layers

Method of selectively alloying interconnect regions by deposition process

Life of this patent

Method of selectively alloying interconnect regions by deposition process

Life of this patent

Abstract

Claims19