Method for manufacturing semiconductor device having increased effective channel length

A method for manufacturing a semiconductor device, the method comprising:

• forming a plurality of gate structures including gate electrodes and insulating layers covering the gate electrodes on a semiconductor substrate;
• implanting impurity ions at a low dose to initially form a source/drain region into the semiconductor substrate, using the gate structures as a mask;
• forming first insulating spacers on the sidewalls of the gate structures;
• forming a planarized interlayer insulating layer pattern on the gate structures, the planarized interlayer insulating layer pattern having holes therein to expose the low dose impurity ion implanted semiconductor device;
• forming second insulating spacers on sidewalls of the interlayer insulating layer pattern and on sidewalls of the first insulating spacers;
• implanting impurity ions at a high dose to completely form the source/drain region into the semiconductor substrate, using the interlayer insulating layer pattern and the second insulating spacers as a mask;
• and
• removing the second insulating spacers.

A method for manufacturing a semiconductor device, the method comprising:

• providing a semiconductor substrate having a first region to form channels therein and a second region to form a source/drain region;
• forming gate electrodes on the first region;
• implanting impurity ions at a low dose into the second region, using the gate electrodes as a mask;
• forming first insulating spacers on sidewalls of the gate electrodes to expose the second region to a first width in a first direction orthogonal to a lengthwise direction of the gate electrodes;
• forming a planarized interlayer insulating layer pattern on the gate electrodes, the planarized interlayer insulating layer having holes therein to expose the first insulating spacers;
• forming second insulating spacers on sidewalls of the interlayer insulating layer pattern and on sidewalls of the first insulating spacers to expose the second region to a second width, which is narrower than the first width;
• implanting impurity ions at a high dose into the second region, using the interlayer insulating layer pattern and the second insulating spacers as a mask;
• and
• removing the second insulating spacers to expose the second region to the first width.